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Sunmin Jang - IEEE Xplore Author Profile

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Author details

Sunmin Jang

Publications

8

Citations

128

Publications by Year

20172020

Co-Authors:

John BellHyungil ChaeThomas ChenKyojin D. ChooM. Batuhan Dayanik

Show All Co-Authors (12)

Sunmin Jang

Affiliation

Apple

Cupertino

CA, USA

Publication Topics

Digital Beamforming,
Beampattern,
Bitstream,
Quantization Noise,
Array Gain,
Digital Delay,
Phase Shift,
Power Consumption,
Prototype,
Adaptive Beamforming,
Analog Beamforming,
Analog-to-digital Converter

Biography

Sunmin Jang (S’14) was born in Seoul, South Korea, in 1987. He received the B.S. degree in electrical engineering from Seoul National University, Seoul, in 2013, the M.S. degree in electrical engineering from the University of Michigan, Ann Arbor, MI, USA, in 2015, where he is currently pursuing the Ph.D. degree, with a focus on digital beamformers.,In 2018, he joined Apple Inc., Sunnyvale, CA, USA.,Mr. Jang received the Jeongsong Scholarship in 2013 and the Samsung Scholarship in 2015.(Based on document published on 14 February 2019).

Publications

8

Citations

128

Publications by Year

20172020

Co-Authors:

John Bell
Hyungil Chae
Thomas Chen
Kyojin D. Choo
M. Batuhan Dayanik

Show All Co-Authors (12)

Author's Published Works

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Showing 1-8 of 8 results

Conferences (5)

Journals (3)

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Single Year
Michael P. Flynn(8)
Sunmin Jang(8)
Rundao Lu(6)
Jaehun Jeong(5)
Daniel Weyer(2)
Broadcom, Irvine, CA, USA(4)
University of Michigan, Ann Arbor, MI, USA(3)
Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI, USA(3)
University of Michigan, Ann Arbor, USA(1)
Silicon Labs, Austin, TX, USA(1)
IEEE Journal of Solid-State Circuits(2)
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)(1)
2018 IEEE International Solid-State Circuits Conference - (ISSCC)(1)
2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)(1)
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)(1)
IEEE(8)
Boston, MA, USA(2)
Honolulu, HI, USA(1)
Philadelphia, PA, USA(1)
San Francisco, CA, USA(1)
Digital Beamforming(6)
Beampattern(5)
Bitstream(4)
Power Consumption(4)
Quantization Noise(4)

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Continuous-Time Bandpass Delta-Sigma Modulators and Bitstream Processing: (Invited)

Michael P. Flynn;Jaehun Jeong;Sunmin Jang;Hyungil Chae;Daniel Weyer;Rundao Lu;John Bell

2020 IEEE Custom Integrated Circuits Conference (CICC)

Year: 2020 | Conference Paper |

Cited by: Papers (1)

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Continuous-Time Bandpass Delta-Sigma Modulators (CTBPDSMs) are effective for IF sampling and simplify receiver design. Bitstream processing (BSP) can be combined with an array of CTBPDSMs to enable highly area and power efficient digital beamforming. BSP directly processes the raw bit-stream outputs of the quantizers, enabling digital processing with simple MUXs. The combination of BSP and CTBPDSM...Show More

Continuous-Time Bandpass Delta-Sigma Modulators and Bitstream Processing: (Invited)

Michael P. Flynn;Jaehun Jeong;Sunmin Jang;Hyungil Chae;Daniel Weyer;Rundao Lu;John Bell

2020 IEEE Custom Integrated Circuits Conference (CICC)

Year: 2020 | Conference Paper |

A 77dB-SFDR Multi-Phase-Sampling 16-Element Digital Beamformer with 64 4GS/s 100MHz-BW Continuous-Time Band-Pass ΔΣ ADCs

Rundao Lu;Sunmin Jang;Yun Hao;Michael P. Flynn

2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

Year: 2019 | Conference Paper |

Cited by: Papers (3)

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This paper tackles the fundamental limitation of distortion in large-scale digital beamforming. SNR improves by 3dB for every doubling of array size; however, distortion is correlated and so is not improved by the array gain. This work introduces the concept of multiple ADCs per element, with each sampling at a different phase, to both reduce distortion of the ADCs and RF frontend. A further advan...Show More

A 77dB-SFDR Multi-Phase-Sampling 16-Element Digital Beamformer with 64 4GS/s 100MHz-BW Continuous-Time Band-Pass ΔΣ ADCs

Rundao Lu;Sunmin Jang;Yun Hao;Michael P. Flynn

2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

Year: 2019 | Conference Paper |

A 1-GHz 16-Element Four-Beam True-Time-Delay Digital Beamformer

Sunmin Jang;Rundao Lu;Jaehun Jeong;Michael P. Flynn

IEEE Journal of Solid-State Circuits

Year: 2019 | Volume: 54, Issue: 5 | Journal Article |

Cited by: Papers (49)

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Phased arrays are widely used due to their low power and small area usage. However, phased arrays depend on the narrowband assumption and, therefore, are not suitable for high-bandwidth applications. Emerging communication standards require increasingly higher bandwidths for improved data rates, which results in a need for timed arrays. However, high power consumption and large area requirements a...Show More

A 1-GHz 16-Element Four-Beam True-Time-Delay Digital Beamformer

Sunmin Jang;Rundao Lu;Jaehun Jeong;Michael P. Flynn

IEEE Journal of Solid-State Circuits

Year: 2019 | Volume: 54, Issue: 5 | Journal Article |

A True Time Delay 16-Element 4-Beam Digital Beamformer

Sunmin Jang;Rundao Lu;Jaehun Jeong;Michael P. Flynn

2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

Year: 2018 | Conference Paper |

Cited by: Papers (13)

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Large phased arrays are limited by inaccurate beam steering (squinting) and by distortion in analog-to-digital conversion. This paper introduces the first integrated digital true time delay beamforming receiver. The true time delay eliminates squinting, making it ideal for large-array wide-bandwidth applications. The beamformer incorporates a new current-steering DAC architecture providing a const...Show More

A True Time Delay 16-Element 4-Beam Digital Beamformer

Sunmin Jang;Rundao Lu;Jaehun Jeong;Michael P. Flynn

2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

Year: 2018 | Conference Paper |

A 36.3-to-38.2GHz −216dBc/Hz2 40nm CMOS fractional-N FMCW chirp synthesizer PLL with a continuous-time bandpass delta-sigma time-to-digital converter

Daniel Weyer;M. Batuhan Dayanik;Sunmin Jang;Michael P. Flynn

2018 IEEE International Solid-State Circuits Conference - (ISSCC)

Year: 2018 | Conference Paper |

Cited by: Papers (26)

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Automotive radar and other mm-wave applications require high-quality frequency synthesizers that offer fast settling and low phase noise. Analog PLLs still dominate in the mm-wave range, but all-digital PLLs (ADPLLs) promise greater flexibility and area efficiency. However, existing mm-wave ADPLLs are large, fail to offer low in-band phase noise [1] or must rely on extensive calibration [2]. Perfo...Show More

A 36.3-to-38.2GHz −216dBc/Hz2 40nm CMOS fractional-N FMCW chirp synthesizer PLL with a continuous-time bandpass delta-sigma time-to-digital converter

Daniel Weyer;M. Batuhan Dayanik;Sunmin Jang;Michael P. Flynn

2018 IEEE International Solid-State Circuits Conference - (ISSCC)

Year: 2018 | Conference Paper |

A 16-Element 4-Beam 1 GHz IF 100 MHz Bandwidth Interleaved Bit Stream Digital Beamformer in 40 nm CMOS

Sunmin Jang;Jaehun Jeong;Rundao Lu;Michael P. Flynn

IEEE Journal of Solid-State Circuits

Year: 2018 | Volume: 53, Issue: 5 | Journal Article |

Cited by: Papers (21)

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A 1 GHz intermediate frequency, 16-element, 4-beam digital beamformer facilitates multi-in multi-out, 5G mobile, and other emerging communication standards. Digital beamforming has been limited by high power consumption, large die area, and the need for a large number of analog-to-digital converters (ADCs). The proposed digital beamformer addresses these issues by combining interleaved bit stream ...Show More

A 16-Element 4-Beam 1 GHz IF 100 MHz Bandwidth Interleaved Bit Stream Digital Beamformer in 40 nm CMOS

Sunmin Jang;Jaehun Jeong;Rundao Lu;Michael P. Flynn

IEEE Journal of Solid-State Circuits

Year: 2018 | Volume: 53, Issue: 5 | Journal Article |

A Maximum-Likelihood Sequence Detection Powered ADC-Based Serial Link

Shiming Song;Kyojin D. Choo;Thomas Chen;Sunmin Jang;Michael P. Flynn;Zhengya Zhang

IEEE Transactions on Circuits and Systems I: Regular Papers

Year: 2018 | Volume: 65, Issue: 7 | Journal Article |

Cited by: Papers (13)

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A 0.88 mm2 65-nm analog-to-digital converter (ADC)-based serial link transceiver is designed with a maximum-likelihood sequence detector (MLSD) for robust equalization. The MLSD is optimized in a pipelined look-ahead architecture to reach 10 Gb/s at 5.8 pJ/b and 5 Gb/s at 3.9 pJ/b, making it practical for an energy-efficient ADC-based serial link. Compared with linear equalizer and decision feedba...Show More

A Maximum-Likelihood Sequence Detection Powered ADC-Based Serial Link

Shiming Song;Kyojin D. Choo;Thomas Chen;Sunmin Jang;Michael P. Flynn;Zhengya Zhang

IEEE Transactions on Circuits and Systems I: Regular Papers

Year: 2018 | Volume: 65, Issue: 7 | Journal Article |

A 16-element 4-beam 1GHz-IF 100MHz-bandwidth Interleaved Bit-Stream digital beamformer in 40nm CMOS

Sunmin Jang;Jaehun Jeong;Rundao Lu;Michael P. Flynn

2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

Year: 2017 | Conference Paper |

Cited by: Papers (2)

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This paper introduces a 16 element, 1GHz IF input, digital beamformer (DBF) that generates 4 independent simultaneous beams, with 100MHz bandwidth. Although DBF has several advantages over analog beamforming, including higher accuracy and multiple beam generation, application of on-chip DBF has been limited due to high power consumption and large die area. The proposed architecture addresses these...Show More

A 16-element 4-beam 1GHz-IF 100MHz-bandwidth Interleaved Bit-Stream digital beamformer in 40nm CMOS

Sunmin Jang;Jaehun Jeong;Rundao Lu;Michael P. Flynn

2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

Year: 2017 | Conference Paper |

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