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Zhenman Fang

Publications
46
Citations
800
Publications by Year
20152024
Co-Authors:
Show All Co-Authors (95)
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Zhenman Fang

Affiliation

Simon Fraser University

Publication Topics

Biography

Zhenman Fang (Member, IEEE) received the Ph.D. degree in computer science from Fudan University, Shanghai, China, in 2014.,He did his post-doctoral research at the University of California at Los Angeles (UCLA), Los Angeles, CA, USA, from 2014 to 2017. He worked as a Staff Software Engineer with Xilinx, San Jose, CA, USA, from 2017 to 2019. He is currently an Assistant Professor with the School of Engineering Science, Simon Fraser University, Burnaby, BC, Canada. His recent research focuses on customizable computing with specialized hardware acceleration, including emerging application characterization and acceleration, novel accelerator-rich and near-data computing architecture designs, and corresponding programming, runtime, and tool supp...
Publications
46
Citations
800
Publications by Year
20152024
Co-Authors:
Show All Co-Authors (95)
Author's Published Works

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SDA: Low-Bit Stable Diffusion Acceleration on Edge FPGAs

Geng Yang;Yanyue Xie;Zhong Jia Xue;Sung-En Chang;Yanyu Li;Peiyan Dong;Jie Lei;Weiying Xie;Yanzhi Wang;Xue Lin;Zhenman Fang

2024 34th International Conference on Field-Programmable Logic and Applications (FPL)
Year: 2024 | Conference Paper |
This paper introduces SDA, the first effort to adapt the expensive stable diffusion (SD) model for edge FPGA deployment. First, we apply quantization-aware training to quantize its weights to 4 -bit and activations to 8 -bit ($W 4 A 8$) with a negligible accuracy loss. Based on that, we propose a high-performance hybrid systolic array (hybridSA) architecture that natively executes convolution and ...Show More

SDA: Low-Bit Stable Diffusion Acceleration on Edge FPGAs

Geng Yang;Yanyue Xie;Zhong Jia Xue;Sung-En Chang;Yanyu Li;Peiyan Dong;Jie Lei;Weiying Xie;Yanzhi Wang;Xue Lin;Zhenman Fang

Year: 2024 | Conference Paper |

SERI: High-Throughput Streaming Acceleration of Electron Repulsion Integral Computation in Quantum Chemistry using HBM-based FPGAs

Philip Stachura;Guanyu Li;Xin Wu;Christian Plessl;Zhenman Fang

2024 34th International Conference on Field-Programmable Logic and Applications (FPL)
Year: 2024 | Conference Paper |
The computation of electron repulsion integrals (ERIs) is a key component for quantum chemical methods. The intensive computation and bandwidth demand for ERI evaluation presents a significant challenge for quantum-mechanics-based atomistic simulations with hybrid density functional theory: due to the tens of trillions of ERI computations in each time step, practical applications are usually limit...Show More

SERI: High-Throughput Streaming Acceleration of Electron Repulsion Integral Computation in Quantum Chemistry using HBM-based FPGAs

Philip Stachura;Guanyu Li;Xin Wu;Christian Plessl;Zhenman Fang

Year: 2024 | Conference Paper |

FORC: A High-Throughput Streaming FPGA Accelerator for Optimized Row Columnar File Decoders in Big Data Engines

Abdul Wadood;Alec Lu;Ken Zhang;Zhenman Fang

2024 34th International Conference on Field-Programmable Logic and Applications (FPL)
Year: 2024 | Conference Paper |
To improve the file storage efficiency of large datasets, big data analytics usually use some common file formats, such as Apache ORC (optimized row columnar) format, to encode and compress the data. However, this shifts the IO bottleneck (especially with high-bandwidth SSDs) to the computation bottleneck on CPUs to decompress and decode the data. This paper presents FORC, a high-throughput stream...Show More

FORC: A High-Throughput Streaming FPGA Accelerator for Optimized Row Columnar File Decoders in Big Data Engines

Abdul Wadood;Alec Lu;Ken Zhang;Zhenman Fang

Year: 2024 | Conference Paper |

BitBlender: Scalable Bloom Filter Acceleration on FPGAs with Dynamic Scheduling

Kenneth Liu;Alec Lu;Zhenman Fang

2024 34th International Conference on Field-Programmable Logic and Applications (FPL)
Year: 2024 | Conference Paper |
The Bloom filter is one of the most widely used data structures in big data analytics to efficiently filter out vast amounts of noisy data. Unfortunately, prior Bloom filter designs only focus on single-input-stream acceleration, and can no longer match the increasing data rates offered by modern networks.To support large Bloom filters with low false-positive rate and high throughput, we present B...Show More

BitBlender: Scalable Bloom Filter Acceleration on FPGAs with Dynamic Scheduling

Kenneth Liu;Alec Lu;Zhenman Fang

Year: 2024 | Conference Paper |

SA4: A Comprehensive Analysis and Optimization of Systolic Array Architecture for 4-bit Convolutions

Geng Yang;Jie Lei;Zhenman Fang;Jiaqing Zhang;Junrong Zhang;Weiying Xie;Yunsong Li

2024 34th International Conference on Field-Programmable Logic and Applications (FPL)
Year: 2024 | Conference Paper |
Many studies have demonstrated that 4-bit precision quantization can maintain accuracy levels comparable to those of floating-point deep neural networks (DNNs). Thus, it has sparked a keen interest in the efficient acceleration of such compressed DNNs, especially 4-bit convolutions, on edge devices. However, we observe that conventional systolic array (SA) architectures, widely adopted for DNN acc...Show More

SA4: A Comprehensive Analysis and Optimization of Systolic Array Architecture for 4-bit Convolutions

Geng Yang;Jie Lei;Zhenman Fang;Jiaqing Zhang;Junrong Zhang;Weiying Xie;Yunsong Li

Year: 2024 | Conference Paper |

HiTC: High-Performance Triangle Counting on HBM-Equipped FPGAs Using HLS

Junzhe Liang;Manoj B. Rajashekar;Xingyu Tian;Zhenman Fang

2024 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM)
Year: 2024 | Conference Paper |
Triangle counting (TC) is one of the fundamental computing patterns in graph computing and social networks. Due to its high memory-to-computation ratio and random memory access patterns, it is nontrivial to accelerate TC's performance. In this work, we propose a high-performance TC (HiTC) accelerator to speed up triangle counting on high-bandwidth memory (HBM)-equipped FPGAs via software/hardware ...Show More

HiTC: High-Performance Triangle Counting on HBM-Equipped FPGAs Using HLS

Junzhe Liang;Manoj B. Rajashekar;Xingyu Tian;Zhenman Fang

Year: 2024 | Conference Paper |

Fast and High-Performance Learned Image Compression With Improved Checkerboard Context Model, Deformable Residual Module, and Knowledge Distillation

Haisheng Fu;Feng Liang;Jie Liang;Yongqiang Wang;Zhenman Fang;Guohe Zhang;Jingning Han

IEEE Transactions on Image Processing
Year: 2024 | Volume: 33 | Journal Article |
Cited by: Papers (2)
Deep learning-based image compression has made great progresses recently. However, some leading schemes use serial context-adaptive entropy model to improve the rate-distortion (R-D) performance, which is very slow. In addition, the complexities of the encoding and decoding networks are quite high and not suitable for many practical applications. In this paper, we propose four techniques to balanc...Show More

Fast and High-Performance Learned Image Compression With Improved Checkerboard Context Model, Deformable Residual Module, and Knowledge Distillation

Haisheng Fu;Feng Liang;Jie Liang;Yongqiang Wang;Zhenman Fang;Guohe Zhang;Jingning Han

Year: 2024 | Volume: 33 | Journal Article |

Learned Image Compression with Dual-Branch Encoder and Conditional Information Coding

Haisheng Fu;Feng Liang;Jie Liang;Zhenman Fang;Guohe Zhang;Jingning Han

2024 Data Compression Conference (DCC)
Year: 2024 | Conference Paper |
Cited by: Papers (1)
Recent advancements in deep learning-based image compression are notable. However, prevalent schemes that employ a serial context-adaptive entropy model to enhance rate-distortion (R-D) performance are markedly slow. Furthermore, the complexities of the encoding and decoding networks are substantially high, rendering them unsuitable for some practical applications. In this paper, we propose two te...Show More

Learned Image Compression with Dual-Branch Encoder and Conditional Information Coding

Haisheng Fu;Feng Liang;Jie Liang;Zhenman Fang;Guohe Zhang;Jingning Han

Year: 2024 | Conference Paper |

Efficient Learned Image Compression with Selective Kernel Residual Module and Channel-Wise Causal Context Model

Haisheng Fu;Feng Liang;Jie Liang;Zhenman Fang;Guohe Zhang;Jingning Han

ICASSP 2024 - 2024 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)
Year: 2024 | Conference Paper |
Cited by: Papers (2)
Recently, learning-based image compression approaches have achieved superior performance over classical image compression methods. However, their complexities remain quite high. In this paper, we propose two efficient modules to reduce the complexity. First, we introduce a selective kernel residual module into the core network, which effectively expands the receptive field and captures global info...Show More

Efficient Learned Image Compression with Selective Kernel Residual Module and Channel-Wise Causal Context Model

Haisheng Fu;Feng Liang;Jie Liang;Zhenman Fang;Guohe Zhang;Jingning Han

Year: 2024 | Conference Paper |

Journal Track Paper ICFPT 2023 : HyBNN: Quantifying and Optimizing Hardware Efficiency of Binary Neural Networks

Geng Yang;Jie Lei;Zhenman Fang;Yunsong Li;Jiaqing Zhang;Weiying Xie

2023 International Conference on Field Programmable Technology (ICFPT)
Year: 2023 | Conference Paper |
Binary neural network (BNN), where both the weight and the activation values are represented with one bit, provides an attractive alternative to deploy highly efficient deep learning inference on resource-constrained edge devices. However, our investigation reveals that, to achieve satisfactory accuracy gains, state-of-the-art (SOTA) BNNs, such as FracBNN and ReActNet, usually have to incorporate ...Show More

Journal Track Paper ICFPT 2023 : HyBNN: Quantifying and Optimizing Hardware Efficiency of Binary Neural Networks

Geng Yang;Jie Lei;Zhenman Fang;Yunsong Li;Jiaqing Zhang;Weiying Xie

Year: 2023 | Conference Paper |

SQL2FPGA: Automatic Acceleration of SQL Query Processing on Modern CPU-FPGA Platforms

Alec Lu;Zhenman Fang

2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
Year: 2023 | Conference Paper |
Cited by: Papers (3)
Today's big data query engines are constantly under pressure to keep up with the rapidly increasing demand for faster processing of more complex workloads. In the past few years, FPGA-based database acceleration efforts have demon-strated promising performance improvement with good energy efficiency. However, few studies target the programming and design automation support to leverage the FPGA acc...Show More

SQL2FPGA: Automatic Acceleration of SQL Query Processing on Modern CPU-FPGA Platforms

Alec Lu;Zhenman Fang

Year: 2023 | Conference Paper |

PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs

Moazin Khatti;Xingyu Tian;Yuze Chi;Licheng Guo;Jason Cong;Zhenman Fang

2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
Year: 2023 | Conference Paper |
Cited by: Papers (4)
In recent years, there has been increasing adoption of FPGAs in datacenters as hardware accelerators, where a large population of end users are software developers. While high-level synthesis (HLS) facilitates software programming, it is still challenging to scale large accelerator designs on modern datacenter FPGAs that often consist of multiple dies and memory banks. More specifically, routing c...Show More

PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs

Moazin Khatti;Xingyu Tian;Yuze Chi;Licheng Guo;Jason Cong;Zhenman Fang

Year: 2023 | Conference Paper |

HyBNN: Quantifying and Optimizing Hardware Efficiency of Binary Neural Networks

Geng Yang;Jie Lei;Zhenman Fang;Yunsong Li;Jiaqing Zhang;Weiying Xie

2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
Year: 2023 | Conference Paper |
Binary neural network (BNN) has recently presented a promising opportunity for deep learning inferences on resource-constrained edge devices. Using extreme data precision, i.e., 1-bit weight and 1-bit activation, BNN not only significantly reduces the network memory footprint, but also trades massive multiply-accumulate operations for much cheaper logical XNOR and population count operations. Howe...Show More

HyBNN: Quantifying and Optimizing Hardware Efficiency of Binary Neural Networks

Geng Yang;Jie Lei;Zhenman Fang;Yunsong Li;Jiaqing Zhang;Weiying Xie

Year: 2023 | Conference Paper |

ESRU: Extremely Low-Bit and Hardware-Efficient Stochastic Rounding Unit Design for Low-Bit DNN Training

Sung-En Chang;Geng Yuan;Alec Lu;Mengshu Sun;Yanyu Li;Xiaolong Ma;Zhengang Li;Yanyue Xie;Minghai Qin;Xue Lin;Zhenman Fang;Yanzhi Wang

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Year: 2023 | Conference Paper |
Cited by: Papers (3)
Stochastic rounding is crucial in the low-bit (e.g., 8-bit) training of deep neural networks (DNNs) to achieve high accuracy. One of the drawbacks of prior studies is that they require a large number of high-precision stochastic rounding units (SRUs) to guarantee low-bit DNN accuracy, which involves considerable hardware overhead. In this paper, we use extremely low-bit SRUs (ESRUs) to save a larg...Show More

ESRU: Extremely Low-Bit and Hardware-Efficient Stochastic Rounding Unit Design for Low-Bit DNN Training

Sung-En Chang;Geng Yuan;Alec Lu;Mengshu Sun;Yanyu Li;Xiaolong Ma;Zhengang Li;Yanyue Xie;Minghai Qin;Xue Lin;Zhenman Fang;Yanzhi Wang

Year: 2023 | Conference Paper |

HeatViT: Hardware-Efficient Adaptive Token Pruning for Vision Transformers

Peiyan Dong;Mengshu Sun;Alec Lu;Yanyue Xie;Kenneth Liu;Zhenglun Kong;Xin Meng;Zhengang Li;Xue Lin;Zhenman Fang;Yanzhi Wang

2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)
Year: 2023 | Conference Paper |
Cited by: Papers (24)
While vision transformers (ViTs) have continuously achieved new milestones in the field of computer vision, their sophisticated network architectures with high computation and memory costs have impeded their deployment on resource-limited edge devices. In this paper, we propose a hardware-efficient image-adaptive token pruning framework called HeatViT for efficient yet accurate ViT acceleration on...Show More

HeatViT: Hardware-Efficient Adaptive Token Pruning for Vision Transformers

Peiyan Dong;Mengshu Sun;Alec Lu;Yanyue Xie;Kenneth Liu;Zhenglun Kong;Xin Meng;Zhengang Li;Xue Lin;Zhenman Fang;Yanzhi Wang

Year: 2023 | Conference Paper |

SuperYOLO: Super Resolution Assisted Object Detection in Multimodal Remote Sensing Imagery

Jiaqing Zhang;Jie Lei;Weiying Xie;Zhenman Fang;Yunsong Li;Qian Du

IEEE Transactions on Geoscience and Remote Sensing
Year: 2023 | Volume: 61 | Journal Article |
Cited by: Papers (115)
Accurately and timely detecting multiscale small objects that contain tens of pixels from remote sensing images (RSI) remains challenging. Most of the existing solutions primarily design complex deep neural networks to learn strong feature representations for objects separated from the background, which often results in a heavy computation burden. In this article, we propose an accurate yet fast o...Show More

SuperYOLO: Super Resolution Assisted Object Detection in Multimodal Remote Sensing Imagery

Jiaqing Zhang;Jie Lei;Weiying Xie;Zhenman Fang;Yunsong Li;Qian Du

Year: 2023 | Volume: 61 | Journal Article |

TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-Based FPGAs

Weikang Qiao;Licheng Guo;Zhenman Fang;Mau-Chung Frank Chang;Jason Cong

IEEE Transactions on Emerging Topics in Computing
Year: 2023 | Volume: 11, Issue: 2 | Journal Article |
Cited by: Papers (4)
The emergence of high-bandwidth memory (HBM) brings new opportunities to boost the performance of sorting acceleration on FPGAs, which was conventionally bounded by the available off-chip memory bandwidth. However, it is nontrivial for designers to fully utilize this immense bandwidth. First, the existing sorter designs cannot be directly scaled at the increasing rate of available off-chip bandwid...Show More

TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-Based FPGAs

Weikang Qiao;Licheng Guo;Zhenman Fang;Mau-Chung Frank Chang;Jason Cong

Year: 2023 | Volume: 11, Issue: 2 | Journal Article |

Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization

Zhengang Li;Mengshu Sun;Alec Lu;Haoyu Ma;Geng Yuan;Yanyue Xie;Hao Tang;Yanyu Li;Miriam Leeser;Zhangyang Wang;Xue Lin;Zhenman Fang

2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)
Year: 2022 | Conference Paper |
Cited by: Papers (36)
Vision transformers (ViTs) are emerging with significantly improved accuracy in computer vision tasks. However, their complex architecture and enormous computation/storage demand impose urgent needs for new hardware accelerator design methodology. This work proposes an FPGA-aware automatic ViT acceleration framework based on the proposed mixed-scheme quantization. To the best of our knowledge, thi...Show More

Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization

Zhengang Li;Mengshu Sun;Alec Lu;Haoyu Ma;Geng Yuan;Yanyue Xie;Hao Tang;Yanyu Li;Miriam Leeser;Zhangyang Wang;Xue Lin;Zhenman Fang

Year: 2022 | Conference Paper |

A Majority-based Approximate Adder for FPGAs

Behnam Ghavami;Mahdi Sajedi;Mohsen Raji;Zhenman Fang;Lesley Shannon

2022 25th Euromicro Conference on Digital System Design (DSD)
Year: 2022 | Conference Paper |
Cited by: Papers (1)
The most advanced ASIC-based approximate adders are focused on gate or transistor level approximating structures. However, due to architectural differences between ASIC and FPGA, comparable performance gains for FPGA-based approximate adders cannot be obtained using ASIC-based approximation ones. In this paper, we propose a method for designing a low-error approximate adder that effectively deploy...Show More

A Majority-based Approximate Adder for FPGAs

Behnam Ghavami;Mahdi Sajedi;Mohsen Raji;Zhenman Fang;Lesley Shannon

Year: 2022 | Conference Paper |

Blind Data Adversarial Bit-flip Attack against Deep Neural Networks

Behnam Ghavami;Mani Sadati;Mohammad Shahidzadeh;Zhenman Fang;Lesley Shannon

2022 25th Euromicro Conference on Digital System Design (DSD)
Year: 2022 | Conference Paper |
Cited by: Papers (3)
Because of their high accuracy, deep neural net-works (DNNs) have achieved amazing success in security-critical systems such as medical devices. It has recently been demon-strated that Adversarial Bit Flip Attacks (BFAs) against DNN hardware by flipping a very small number of bits can result in catastrophic accuracy loss. The reliance on test data, however, is a significant drawback of previous st...Show More

Blind Data Adversarial Bit-flip Attack against Deep Neural Networks

Behnam Ghavami;Mani Sadati;Mohammad Shahidzadeh;Zhenman Fang;Lesley Shannon

Year: 2022 | Conference Paper |

Stealthy Attack on Algorithmic-Protected DNNs via Smart Bit Flipping

Behnam Ghavami;Seyd Movi;Zhenman Fang;Lesley Shannon

2022 23rd International Symposium on Quality Electronic Design (ISQED)
Year: 2022 | Conference Paper |
Cited by: Papers (4)
Recently, deep neural networks (DNNs) have been deployed in safety-critical systems such as autonomous vehicles and medical devices. Shortly after that, the vulnerability of DNNs were revealed by stealthy adversarial examples where crafted inputs—by adding tiny perturbations to original inputs—can lead a DNN to generate misclassification outputs. To improve the robustness of DNNs, some algorithmic...Show More

Stealthy Attack on Algorithmic-Protected DNNs via Smart Bit Flipping

Behnam Ghavami;Seyd Movi;Zhenman Fang;Lesley Shannon

Year: 2022 | Conference Paper |

TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-based FPGAs

Weikang Qiao;Licheng Guo;Zhenman Fang;Mau-Chung Frank Chang;Jason Cong

2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
Year: 2022 | Conference Paper |
Cited by: Papers (2)
The emergence of high-bandwidth memory (HBM) brings new opportunities to boost the performance of sorting acceleration on FPGAs, which was conventionally bounded by the available off-chip memory bandwidth. However, it is nontrivial for designers to fully utilize this immense bandwidth. First, the existing sorter designs cannot be directly scaled at the increasing rate of available off-chip bandwid...Show More

TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-based FPGAs

Weikang Qiao;Licheng Guo;Zhenman Fang;Mau-Chung Frank Chang;Jason Cong

Year: 2022 | Conference Paper |

FitAct: Error Resilient Deep Neural Networks via Fine-Grained Post-Trainable Activation Functions

Behnam Ghavami;Mani Sadati;Zhenman Fang;Lesley Shannon

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Year: 2022 | Conference Paper |
Cited by: Papers (17)
Deep neural networks (DNNs) are increasingly being deployed in safety-critical systems such as personal healthcare devices and self-driving cars. In such DNN-based systems, error resilience is a top priority since faults in DNN inference could lead to mispredictions and safety hazards. For latency-critical DNN inference on resource-constrained edge devices, it is nontrivial to apply conventional r...Show More

FitAct: Error Resilient Deep Neural Networks via Fine-Grained Post-Trainable Activation Functions

Behnam Ghavami;Mani Sadati;Zhenman Fang;Lesley Shannon

Year: 2022 | Conference Paper |

Algorithm/Hardware Codesign for Real-Time On-Satellite CNN-Based Ship Detection in SAR Imagery

Geng Yang;Jie Lei;Weiying Xie;Zhenman Fang;Yunsong Li;Jiaxuan Wang;Xin Zhang

IEEE Transactions on Geoscience and Remote Sensing
Year: 2022 | Volume: 60 | Journal Article |
Cited by: Papers (15)
Recently, the convolutional neural network (CNN)-based approach for on-satellite ship detection in synthetic aperture radar (SAR) images has received increasing attention since it does not rely on predefined imagery features and distributions that are required in conventional detection methods. To achieve high detection accuracy, most of the existing CNN-based methods leverage complex off-the-shel...Show More

Algorithm/Hardware Codesign for Real-Time On-Satellite CNN-Based Ship Detection in SAR Imagery

Geng Yang;Jie Lei;Weiying Xie;Zhenman Fang;Yunsong Li;Jiaxuan Wang;Xin Zhang

Year: 2022 | Volume: 60 | Journal Article |

MAPLE: A Machine Learning based Aging-Aware FPGA Architecture Exploration Framework

Behnam Ghavami;Milad Ibrahimipour;Zhenman Fang;Lesley Shannon

2021 31st International Conference on Field-Programmable Logic and Applications (FPL)
Year: 2021 | Conference Paper |
Cited by: Papers (2)
In this paper, we develop a framework called MAPLE to enable the aging-aware FPGA architecture exploration. The core idea is to efficiently model the aging-induced delay degradation at the coarse-grained FPGA basic block level using deep neural networks (DNNs). For each type of the FPGA basic block such as LUT and DSP, we first characterize its accurate delay degradation via transistor-level SPICE...Show More

MAPLE: A Machine Learning based Aging-Aware FPGA Architecture Exploration Framework

Behnam Ghavami;Milad Ibrahimipour;Zhenman Fang;Lesley Shannon

Year: 2021 | Conference Paper |

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