Loading web-font TeX/Main/Regular

Chaogui Kang - IEEE Xplore Author Profile

Scheduled Maintenance on Monday 1/13/2025

Single article sales and account management will be unavailable from 5:00 AM - 7:00 PM ET (09:00 - 23:00 UTC). We apologize for the inconvenience.

IEEE.org
IEEE Xplore
IEEE SA
IEEE Spectrum
More Sites

- Donate
- Personal Sign In

Institutional Sign In

Institutional Sign In

ADVANCED SEARCH

Author details

Chaogui Kang

Publications

6

Citations

100

Publications by Year

20102024

Co-Authors:

Ximeng ChengDongwan FanSong GaoJianya GongBo Huang

Show All Co-Authors (18)

Chaogui Kang

Affiliation

National Engineering Research Center of Geographic Information System

China University of Geosciences (Wuhan)

Wuhan, China

Publication Topics

Functional Zones,
Human Activities,
Remote Sensing,
Urban Functions,
Urbanization,
Artificial Intelligence Models,
Big Data,
Building Height,
Cellular Automata Model,
Census Tracts,
Chinese Restaurant,
Cities In China

Biography

Chaogui Kang (kangchaogui@cug.edu.cn) is with the National Engineering Research Center of Geographic Information System, China University of Geosciences (Wuhan), Wuhan 430074, China.(Based on document published on 4 January 2024).

Publications

6

Citations

100

Publications by Year

20102024

Co-Authors:

Ximeng Cheng
Dongwan Fan
Song Gao
Jianya Gong
Bo Huang

Show All Co-Authors (18)

Author's Published Works

Search History

Showing 1-12 of 12 results

Conferences (8)

Journals (4)

Sort

Filter Results

Show

Open Access Only

Range
Single Year
Hamidreza Maghami(12)
Pedram Payandehnia(11)
Hossein Mirzaie(8)
Ramin Zanbaghi(6)
Kartikeya Mayaram(6)
School of EECS, Oregon State University, Corvallis, OR, USA(3)
School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR, USA(3)
Electrical and Computer Engineering Department, University of Tehran, Tehran, Iran(2)
Cirrus Logic Inc., Austin, TX, USA(2)
University of Colorado, Boulder, CO, USA(2)
2011 19th Iranian Conference on Electrical Engineering(2)
IEEE Transactions on Circuits and Systems I: Regular Papers(2)
2011 24th Canadian Conference on Electrical and Computer Engineering(CCECE)(1)
2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)(1)
2017 IEEE International Symposium on Circuits and Systems (ISCAS)(1)
IEEE(12)
Media(1)
Tehran, Iran(2)
Austin, TX, USA(1)
Baltimore, MD, USA(1)
College Station, TX, USA(1)
Niagara Falls, ON, Canada(1)
Input Signal(8)
Quantization Noise(7)
Analog-to-digital Converter(6)
Quantum(6)
Time Domain(6)

Select All on Page

Sort By

Results

A Highly Linear OTA-Less 1-1 MASH VCO-Based $\Delta\Sigma$ ADC With an Efficient Phase Quantization Noise Extraction Technique

Hamidreza Maghami;Pedram Payandehnia;Hossein Mirzaie;Ramin Zanbaghi;Hossein Zareie;Justin Goins;Siladitya Dey;Kartikeya Mayaram;Terri S. Fiez

IEEE Journal of Solid-State Circuits

Year: 2020 | Volume: 55, Issue: 3 | Journal Article |

Cited by: Papers (24)

HTML

In this article, an efficient technique is introduced to extract the quantization noise of a multi-phase voltage-controlled oscillator (VCO)-based quantizer (VCOQ) in the time domain as a pulsewidth modulated (PWM) signal. Using this technique, a new highly linear VCO-based 1-1 multi-stage noise shaping (MASH) delta-sigma analog-to-digital converter (ADC) structure is presented. This architecture ...Show More

A Highly Linear OTA-Less 1-1 MASH VCO-Based $\Delta\Sigma$ ADC With an Efficient Phase Quantization Noise Extraction Technique

Hamidreza Maghami;Pedram Payandehnia;Hossein Mirzaie;Ramin Zanbaghi;Hossein Zareie;Justin Goins;Siladitya Dey;Kartikeya Mayaram;Terri S. Fiez

IEEE Journal of Solid-State Circuits

Year: 2020 | Volume: 55, Issue: 3 | Journal Article |

0.9V, 79.7dB SNDR, 2MHz-BW, Highly linear OTA-less 1-1 MASH VCO-based ΔΣ with a Novel Phase Quantization Noise Extraction Technique

Hamidreza Maghami;Pedram Payandehnia;Hossein Mirzaie;Ramin Zanbaghi;Siladitya Dey;Justin Goins;Kartikeya Mayaram;Terri S. Fiez

2019 IEEE Custom Integrated Circuits Conference (CICC)

Year: 2019 | Conference Paper |

Cited by: Papers (2) | Patents (2)

HTML

In this paper a novel technique is introduced to extract the quantization noise of a multi-phase VCO-based quantizer (VCOQ) in the time domain as a PWM signal. Using this technique, a new highly linear VCO-based 1-1 MASH delta-sigma ADC structure is presented. This architecture does not require any OTA-based analog integrators or power hungry linearization methods. The first stage is a closed loop...Show More

0.9V, 79.7dB SNDR, 2MHz-BW, Highly linear OTA-less 1-1 MASH VCO-based ΔΣ with a Novel Phase Quantization Noise Extraction Technique

Hamidreza Maghami;Pedram Payandehnia;Hossein Mirzaie;Ramin Zanbaghi;Siladitya Dey;Justin Goins;Kartikeya Mayaram;Terri S. Fiez

2019 IEEE Custom Integrated Circuits Conference (CICC)

Year: 2019 | Conference Paper |

An Amplifier-Free 0–2 SAR-VCO MASH ΔΣ ADC

Pedram Payandehnia;Hamidreza Maghami;Hossein Mirzaie;Matthew L. Johnston;Gabor. C. Temes

2019 IEEE International Symposium on Circuits and Systems (ISCAS)

Year: 2019 | Conference Paper |

HTML

A 0-2 Multi Stage Noise Shaping (MASH) analog-to-digital converter (ADC) is proposed. A SAR ADC and a VCO-based quantizer (VCOQ) are used in the first stage and second stages, respectively. The VCOQ proposed in this paper achieves second-order noise shaping by employing an error feedback architecture. The error feedback architecture is implemented by extracting the quantization noise of the VCOQ a...Show More

An Amplifier-Free 0–2 SAR-VCO MASH ΔΣ ADC

Pedram Payandehnia;Hamidreza Maghami;Hossein Mirzaie;Matthew L. Johnston;Gabor. C. Temes

2019 IEEE International Symposium on Circuits and Systems (ISCAS)

Year: 2019 | Conference Paper |

A Highly Linear OTA-Free VCO-Based 1-1 MASH $\Delta\Sigma$ ADC

Hamidreza Maghami;Pedram Payandehnia;Hossein Mirzaie;Ramin Zanbaghi;Siladitya Dey;Kartikeya Mayaram;Terri S. Fiez

IEEE Transactions on Circuits and Systems I: Regular Papers

Year: 2019 | Volume: 66, Issue: 7 | Journal Article |

Cited by: Papers (10)

HTML

In this paper, a new voltage-controlled oscillator (VCO)-based 1-1 MASH delta-sigma ADC structure is presented. The proposed architecture does not require any operational transconductance amplifier-based analog integrators or integrating capacitors. Second-order noise shaping is achieved by using a VCO as an integrator in the feedback loop of the first stage and an open-loop VCO quantizer in the s...Show More

A Highly Linear OTA-Free VCO-Based 1-1 MASH $\Delta\Sigma$ ADC

Hamidreza Maghami;Pedram Payandehnia;Hossein Mirzaie;Ramin Zanbaghi;Siladitya Dey;Kartikeya Mayaram;Terri S. Fiez

IEEE Transactions on Circuits and Systems I: Regular Papers

Year: 2019 | Volume: 66, Issue: 7 | Journal Article |

A 72.4-dB SNDR 92-dB SFDR Blocker Tolerant CT $\Delta\Sigma$ Modulator With Inherent DWA

Hossein Mirzaie;Hamidreza Maghami;Ramin Zanbaghi;Pedram Payandehnia;Kartikeya Mayaram;Terri S. Fiez

IEEE Transactions on Circuits and Systems II: Express Briefs

Year: 2019 | Volume: 66, Issue: 3 | Journal Article |

Cited by: Papers (6)

HTML

This brief presents the design and implementation of a new blocker tolerant wideband continuous-time delta-sigma modulator. Using a customized digital integrator with inherent data-weighted averaging at the back-end of the modulator, the power consumption of the quantizer is reduced while the speed of operation is increased. Additionally, by using a single amplifier biquad structure in the loop fi...Show More

A 72.4-dB SNDR 92-dB SFDR Blocker Tolerant CT $\Delta\Sigma$ Modulator With Inherent DWA

Hossein Mirzaie;Hamidreza Maghami;Ramin Zanbaghi;Pedram Payandehnia;Kartikeya Mayaram;Terri S. Fiez

IEEE Transactions on Circuits and Systems II: Express Briefs

Year: 2019 | Volume: 66, Issue: 3 | Journal Article |

A Novel Time-Domain Phase Quantization Noise Extraction for a VCO-based Quantizer

Hamidreza Maghami;Hossein Mirzaie;Pedram Payandehnia;Kartikeya Mayaram;Ramin Zanbaghi;Terri Fiez

2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)

Year: 2018 | Conference Paper |

Cited by: Papers (3)

HTML

A highly linear SAR-VCO MASH delta-sigma ADC architecture is presented. OTA based analog integrators are not needed whereby the ADC is mostly digital and process scaling friendly. A new technique is introduced to extract the quantization noise of the VCO-based quantizer as a PWM signal using digital circuitry. This technique is independent of the OSR and the input signal amplitude of the VCO-based...Show More

A Novel Time-Domain Phase Quantization Noise Extraction for a VCO-based Quantizer

Hamidreza Maghami;Hossein Mirzaie;Pedram Payandehnia;Kartikeya Mayaram;Ramin Zanbaghi;Terri Fiez

2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)

Year: 2018 | Conference Paper |

A 0.49–13.3 MHz Tunable Fourth-Order LPF with Complex Poles Achieving 28.7 dBm OIP3

Pedram Payandehnia;Hamidreza Maghami;Hossein Mirzaie;Manjunath Kareppagoudr;Siladitya Dey;Massoud Tohidian;Gabor C. Temes

IEEE Transactions on Circuits and Systems I: Regular Papers

Year: 2018 | Volume: 65, Issue: 8 | Journal Article |

Cited by: Papers (31)

HTML

A novel switched-capacitor low-pass filter architecture is presented. In the proposed scheme, a feedback path is added to a charge-rotating real-pole filter to implement complex poles. The selectivity is enhanced, and the in-band loss is reduced compared with the real-pole filter. The output thermal noise level and the tuning range are both close to those of the real-pole filter. These features ma...Show More

A 0.49–13.3 MHz Tunable Fourth-Order LPF with Complex Poles Achieving 28.7 dBm OIP3

Pedram Payandehnia;Hamidreza Maghami;Hossein Mirzaie;Manjunath Kareppagoudr;Siladitya Dey;Massoud Tohidian;Gabor C. Temes

IEEE Transactions on Circuits and Systems I: Regular Papers

Year: 2018 | Volume: 65, Issue: 8 | Journal Article |

A highly linear OTA-free VCO-based 1-1 MASH ΔΣ ADC

Hamidreza Maghami;Pedram Payandehnia;Hossein Mirzaie;Kartikeya Mayaram;Ramin Zanbaghi;Terri Fiez

2017 IEEE International Symposium on Circuits and Systems (ISCAS)

Year: 2017 | Conference Paper |

Cited by: Papers (4)

HTML

In this paper a new VCO-based MASH delta-sigma ADC structure is presented. The proposed architecture does not require any OTA-based analog integrators or integrating capacitors. Second-order noise shaping is achieved by using a VCO as an integrator in the feedback loop of the first stage and an open loop VCO quantizer in the second stage. Simple digital circuitry extracts the phase quantization er...Show More

A highly linear OTA-free VCO-based 1-1 MASH ΔΣ ADC

Hamidreza Maghami;Pedram Payandehnia;Hossein Mirzaie;Kartikeya Mayaram;Ramin Zanbaghi;Terri Fiez

2017 IEEE International Symposium on Circuits and Systems (ISCAS)

Year: 2017 | Conference Paper |

Sequential interstage correlated double sampling: A switched-capacitor technique for high accuracy systems

Pedram Payandehnia;Hamidreza Maghami;Xin Meng;Gabor C. Temes;Hirokazu Yoshizawa

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

Year: 2014 | Conference Paper |

Cited by: Papers (1)

HTML

A novel sequential inter-stage correlated double sampling technique has been proposed. This technique provides considerable enhancement in the effective accuracy of a switched-capacitor architecture. Superior accuracy and thermal noise performance is achieved compared to the conventional correlated double sampling technique. The proposed approach provides higher input signal bandwidth by reducing ...Show More

Sequential interstage correlated double sampling: A switched-capacitor technique for high accuracy systems

Pedram Payandehnia;Hamidreza Maghami;Xin Meng;Gabor C. Temes;Hirokazu Yoshizawa

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

Year: 2014 | Conference Paper |

A low power 9.5 ENOB 100MS/s pipeline ADC using correlated level shifting

Kambiz Nanbakhsh;Hamidreza Maghami;Samad Sheikhaei;Nasser Masoumi;Pedram Payandehnia

2011 24th Canadian Conference on Electrical and Computer Engineering(CCECE)

Year: 2011 | Conference Paper |

HTML

In this work the design of a low power 10-bit 100MS/s pipeline ADC is presented. Low power consumption is realized by using an optimum bit per stage resolution and also by applying the correlated level shifting (CLS) technique for the first four stages. Moreover, by obviating the need for a first stage S/H, power consumption was reduced considerably. The first stage of the pipeline has a 2.5-bit r...Show More

A low power 9.5 ENOB 100MS/s pipeline ADC using correlated level shifting

Kambiz Nanbakhsh;Hamidreza Maghami;Samad Sheikhaei;Nasser Masoumi;Pedram Payandehnia

2011 24th Canadian Conference on Electrical and Computer Engineering(CCECE)

Year: 2011 | Conference Paper |

High speed CML latch using active inductor in 0.18μm CMOS technology

Pedram Payandeh Nia;Hamidreza Maghami;Samad Sheikhaei;Aliazam Abbasfar;Behjat Foruzandeh;Kambiz Nanbakhsh

2011 19th Iranian Conference on Electrical Engineering

Year: 2011 | Conference Paper |

In this paper, a high speed latch architecture is proposed. This latch is based on a modified CML architecture, in which the tail current source is removed. To further increase the speed, shunt peaking is used. This technique can be implemented using passive or active inductors. Active inductors require smaller on-chip implementation area, but impose some drawbacks such as nonlinearity and noise. ...Show More

High speed CML latch using active inductor in 0.18μm CMOS technology

Pedram Payandeh Nia;Hamidreza Maghami;Samad Sheikhaei;Aliazam Abbasfar;Behjat Foruzandeh;Kambiz Nanbakhsh

2011 19th Iranian Conference on Electrical Engineering

Year: 2011 | Conference Paper |

High speed CML latch using active inductor in 0.18μm CMOS technology

Pedram Payandehnia;Hamidreza Maghami;Samad Sheikhaei;Aliazam Abbasfar;Behjat Forouzandeh;Kambiz Nanbakhsh

2011 19th Iranian Conference on Electrical Engineering

Year: 2011 | Conference Paper |

Cited by: Papers (1)

HTML

In this paper, a high speed latch architecture is proposed. This latch is based on a modified CML architecture, in which the tail current source is removed. To further increase the speed, shunt peaking is used. This technique can be implemented using passive or active inductors. Active inductors require smaller on-chip implementation area, but impose some drawbacks such as nonlinearity and noise. ...Show More

High speed CML latch using active inductor in 0.18μm CMOS technology

Pedram Payandehnia;Hamidreza Maghami;Samad Sheikhaei;Aliazam Abbasfar;Behjat Forouzandeh;Kambiz Nanbakhsh

2011 19th Iranian Conference on Electrical Engineering

Year: 2011 | Conference Paper |

IEEE Personal Account

Change username/password

Purchase Details

Payment Options
View Purchased Documents

Profile Information

Communications Preferences
Profession and Education
Technical interests

Need Help?

US & Canada: +1 800 678 4333
Worldwide: +1 732 981 0060
Contact & Support

Follow

About IEEE Xplore | Contact Us | Help | Accessibility | Terms of Use | Nondiscrimination Policy | IEEE Ethics Reporting | Sitemap | IEEE Privacy Policy

A public charity, IEEE is the world's largest technical professional organization dedicated to advancing technology for the benefit of humanity.

© Copyright 2025 IEEE - All rights reserved, including rights for text and data mining and training of artificial intelligence and similar technologies.

IEEE Account

Change Username/Password
Update Address

Purchase Details

Payment Options
Order History
View Purchased Documents

Profile Information

Communications Preferences
Profession and Education
Technical Interests

Need Help?

US & Canada: +1 800 678 4333
Worldwide: +1 732 981 0060
Contact & Support

About IEEE Xplore
Contact Us
Help
Accessibility
Terms of Use
Nondiscrimination Policy
Sitemap
Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest technical professional organization dedicated to advancing technology for the benefit of humanity.
© Copyright 2025 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.

Test Whats new message.