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IEEE Transactions on Circuits and Systems I: Regular Papers
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Year: 2022 | Volume: 69 | Issue: 10
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information
Publication Year: 2022,Page(s):C2 - C2
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information
Year: 2022 | Volume: 69 | Issue: 10
Relation Between INL and ACPR of RF DACs
Publication Year: 2022,Page(s):3877 - 3887
Cited by: Papers (2)
The integral nonlinearity of digital-to-analog converters manifests itself as adjacent-channel power in RF transmitters. This paper derives compact equations relating these two quantities and verifies the results by simulations. Both current-steering and switched-mode architectures are analyzed.Show More
Non-Binary Spin Wave Based Circuit Design
Abdulqader Nael Mahmoud;Frederic Vanderveken;Florin Ciubotaru;Christoph Adelmann;Said Hamdioui;Sorin Cotofana
Publication Year: 2022,Page(s):3888 - 3900
Cited by: Papers (2)
By their very nature, Spin Waves (SWs) excited at the same frequency but different amplitudes, propagate through waveguides and interfere with each other at the expense of ultra-low energy consumption. In addition, all (part) of the SW energy can be moved from one waveguide to another by means of coupling effects. In this paper we make use of these SW features and introduce a novel non Boolean alg...Show More
An Equivalent-Time Sampling Millimeter-Wave Ultra-Wideband Radar Pulse Digitizer in CMOS
Publication Year: 2022,Page(s):3901 - 3914
Cited by: Papers (1)
In designing a mm-wave ultra-wideband pulse-Doppler radar IC, one of the main challenges encountered is to reduce the high power consumption of the circuitries in the IC. A direct-RF receiver can be used in the radar’s design to reduce the radar’s power consumption. However, a digitizer that can directly digitize mm-wave ultra-wideband radar pulses is needed to implement such a receiver. This work...Show More
A 0.5–1.7 V Efficient and PVT-Invariant Constant Subthreshold gm Reference Circuit in CMOS
Publication Year: 2022,Page(s):3915 - 3926
Cited by: Papers (7)
This paper presents a low-power constant subthreshold transconductance reference circuit that produces a constant transconductance by subtracting the output currents of two independent transconductance references. By taking the difference between the output currents of the two independent transconductance references, process, voltage and temperature variations are reduced by minimizing the effects...Show More
Robust Timing Error Detection for Multilevel Baud-Rate CDR
Publication Year: 2022,Page(s):3927 - 3939
Cited by: Papers (8)
Baud rate timing recovery, for which the Mueller-Muller approach is the most prominent, has become the mainstay of high speed serial links because of the simplicity of its implementation. The foundations of Mueller-Muller - Type A timing function and its propensity to lock to erroneous sampling points when applied to high order pulse amplitude modulation is studied. Using the timing error detector...Show More
BR-CIM: An Efficient Binary Representation Computation-In-Memory Design
Zhiheng Yue;Yabing Wang;Yubin Qin;Leibo Liu;Shaojun Wei;Shouyi Yin
Publication Year: 2022,Page(s):3940 - 3953
Cited by: Papers (8)
Deep neural network (DNN) has recently attracted tremendous attention in various fields. But the computing operation requirement and the memory bottleneck limit the energy efficiency of hardware implementations. Binary quantization is proposed to relieve the pressure of hardware design. And the Computing-In-Memory (CIM) is regarded as a promising method to resolve the memory wall challenge. Howeve...Show More
A 1.5-GS/s 6-bit Single-Channel Loop-Unrolled SAR ADC With Speculative CDAC Switching Control Technique in 28-nm CMOS
Publication Year: 2022,Page(s):3954 - 3964
Cited by: Papers (2)
This paper presents a 1.5-GS/s 6-bit single-channel loop-unrolled successive approximation register (SAR) analog-to-digital converter (ADC) using speculative capacitive DAC (CDAC) switching control technique. The proposed SAR ADC achieves a high sampling rate by eliminating additional delays in typical loop-unrolled SAR ADCs related to settling time constraints in their CDACs. Specifically, the CD...Show More
A 10-bit 100-MS/s SAR ADC With Always-On Reference Ripple Cancellation
Yi Shen;Xiyuan Tang;Xin Xin;Shubin Liu;Zhangming Zhu;Nan Sun
Publication Year: 2022,Page(s):3965 - 3975
Cited by: Papers (13)
This work presents an always-on reference ripple cancellation technique that actively cancels the reference settling error throughout the entire SAR conversion process. Unlike the conventional designs that require high-speed reference buffers or large on-chip decoupling capacitors to minimize the error, it incorporates an extra path to actively cancel the error, which can provide considerable refe...Show More
A 7-Bit 7-GHz Multiphase Interpolator-Based DPC for CDR Applications
Meysam M. Khanghah;Khosrov D. Sadeghipour;Denis Kelly;Cleitus Antony;Peter Ossieur;Paul D. Townsend
Publication Year: 2022,Page(s):3976 - 3988
Cited by: Papers (4)
This paper presents a 7-bit digital to phase converter (DPC) for high speed clock and data recovery (CDR) applications which is capable of generating multi-phase clocks at 7-GHz frequency. Fabricated in a standard 65-nm CMOS technology, the design introduces a modified phase interpolator (PI) and a quadrature phase corrector (QPC) to reduce the effect of the circuit imperfections on the DPC’s reso...Show More
A Low-Power Indirect Time-of-Flight CMOS Image Sensor With Fixed Depth Noise Compensation and Dual-Mode Imaging for Depth Dynamic Range Enhancement
Canxing Piao;Yeonsoo Ahn;Donguk Kim;Jihoon Park;Jubin Kang;Seong-Jin Kim;Jung-Hoon Chun;Jaehyuk Choi
Publication Year: 2022,Page(s):3989 - 3999
Cited by: Papers (3)
We present a low-power indirect time-of-flight (iTOF) image sensor with fixed depth noise compensation and dual-mode imaging for depth dynamic range (DDR) enhancement. To reduce the power consumption from high-frequency pixel modulation, a TX driver with a single-sided clock chain is employed in the sensor. The inherent phase delay of the clock chain and the delay of the row bus are measured using...Show More
A 32–40 GHz 7-bit Bi-Directional Phase Shifter With 0.36 dB/1.6° RMS Magnitude/Phase Errors for Phased Array Systems
Yongjie Li;Zongming Duan;Yun Fang;Xiao Li;Biao Deng;Yuefei Dai;Liguo Sun;Hao Gao
Publication Year: 2022,Page(s):4000 - 4013
Cited by: Papers (25)
This paper presents a digitally programmable bi-directional 7-bit passive phase shifter in a 65 nm CMOS technology. The core of this passive vector-synthesized phase shifter is a hybrid quadrature generator (HQG), an interstage matching network, and a passive vector modulator (PVM). This work proposes a high coupling-factor-based quadrature generator design methodology and demonstrates it with a c...Show More
SWPU: A 126.04 TFLOPS/W Edge-Device Sparse DNN Training Processor With Dynamic Sub-Structured Weight Pruning
Publication Year: 2022,Page(s):4014 - 4027
Cited by: Papers (8)
When deploying deep neural networks (DNNs), edge devices training is practical to improve model adaptivity for various user-specific scenarios while avoiding privacy disclosure. However, the training computation is intolerable for edge devices. It inspires sparse DNN training (SDT) into the limelight, which reduces training computation by dynamic weight pruning. Generally, SDT has two strategies b...Show More
VSDCA: A Voltage Sensing Differential Column Architecture Based on 1T2R RRAM Array for Computing-in-Memory Accelerators
Publication Year: 2022,Page(s):4028 - 4041
Cited by: Papers (15)
Non-volatile memory (NVM) such as RRAM and PCM has become the key component in high energy efficiency computing-in-memory (CIM) architectures. However, the computing accuracy and energy efficiency improvement of conventional 1T1R RRAM array based current sensing CIM scheme is hindered by device variation and large output current. In this work, we propose a voltage sensing differential column archi...Show More
PL-NPU: An Energy-Efficient Edge-Device DNN Training Processor With Posit-Based Logarithm-Domain Computing
Publication Year: 2022,Page(s):4042 - 4055
Cited by: Papers (8)
Edge device deep neural network (DNN) training is practical to improve model adaptivity for unfamiliar datasets while avoiding privacy disclosure and huge communication cost. Nevertheless, apart from feed-forward (FF) as inference, DNN training still requires back-propagation (BP) and weight gradient (WG), introducing power-consuming floating-point computing requirements, hardware underutilization...Show More
Neural Network Training on In-Memory-Computing Hardware With Radix-4 Gradients
Publication Year: 2022,Page(s):4056 - 4068
Cited by: Papers (1)
Deep learning training involves a large number of operations, which are dominated by high dimensionality Matrix-Vector Multiplies (MVMs). This has motivated hardware accelerators to enhance compute efficiency, but where data movement and accessing are proving to be key bottlenecks. In-Memory Computing (IMC) is an approach with the potential to overcome this, whereby computations are performed in-p...Show More
GQNA: Generic Quantized DNN Accelerator With Weight-Repetition-Aware Activation Aggregating
Jianxun Yang;Fengbin Tu;Yixuan Li;Yiqi Wang;Leibo Liu;Shaojun Wei;Shouyi Yin
Publication Year: 2022,Page(s):4069 - 4082
Cited by: Papers (11)
Quantization is a prominent approach to compress model sizes of deep neural networks (DNNs), which clusters high-precision weights into a smaller set of quantization levels and represents high-precision weights by low-precision indexes. To achieve the same accuracy, nonuniform quantized DNNs (NUQ-DNNs) with unequal quantization intervals need lower index precision than uniform quantized DNNs (UQ-D...Show More
Faster NTRU on ARM Cortex-M4 With TMVP-Based Multiplication
Publication Year: 2022,Page(s):4083 - 4092
Cited by: Papers (8)
This paper focuses on speeding up NTRU - one of the lattice-based finalists of the NIST PQC competition - by improving the ring multiplication. The Number Theoretic Transform (NTT), Toom-Cook, and Karatsuba are the most commonly used algorithms for implementing NTRU. In this paper, we propose Toeplitz matrix-vector product (TMVP) based algorithms for multiplication for all parameter sets of NTRU. ...Show More
An Efficient Implementation of Convolutional Neural Network With CLIP-Q Quantization on FPGA
Publication Year: 2022,Page(s):4093 - 4102
Cited by: Papers (7)
Convolutional neural networks (CNNs) have achieved tremendous success in the computer vision domain recently. The pursue for better model accuracy drives the model size and the storage requirements of CNNs as well as the computational complexity. Therefore, Compression Learning by InParallel Pruning-Quantization (CLIP-Q) was proposed to reduce a vast amount of weight storage requirements by using ...Show More
Multilayer Financial Complex Networks and Their Applications
Publication Year: 2022,Page(s):4103 - 4116
Cited by: Papers (5)
In the context of global integration, the theory of financial complex networks has made significant contributions to the establishment of stable financial systems and effective regulatory systems. This survey paper presents a systematic methodology for the multi-layer financial complex networks and their applications. Several typical financial networks in existing research are first summarized: th...Show More
Analysis and Measurement of Noise Suppression in a Nonlinear Regenerative Amplifier
Publication Year: 2022,Page(s):4117 - 4127
This paper analyzes the ability to suppress in-band noise power of a regenerative amplifier (RA) operating in the nonlinear regime in response to a continuous wave (CW) input tone. As opposed to the linear regime where a CW tone and the noise floor experience the same transfer function, it is shown that the non-linear saturation behavior of an RA yields different transfer characteristics between a...Show More
Chimera States in Neuro-Inspired Area-Efficient Asynchronous Cellular Automata Networks
Karolos-Alexandros Tsakalos;Paraskevi Dragkola;Rafailia-Eleni Karamani;Michail-Antisthenis Tsompanas;Astero Provata;Panagiotis Dimitrakis;Andrew I. Adamatzky;Georgios Ch. Sirakoulis
Publication Year: 2022,Page(s):4128 - 4140
Cited by: Papers (9)
Synchronization transition in neuromorphic networks has attracted much attention recently as a fundamental property of biological neural networks, which relies on network connectivity along with different synaptic features. In this work, an area-optimized FPGA implementation of an Asynchronous Cellular Automata Neuron model that exhibits discrete-state neuron dynamics is introduced. The proposed n...Show More
Chimera States in Neuro-Inspired Area-Efficient Asynchronous Cellular Automata Networks
Karolos-Alexandros Tsakalos;Paraskevi Dragkola;Rafailia-Eleni Karamani;Michail-Antisthenis Tsompanas;Astero Provata;Panagiotis Dimitrakis;Andrew I. Adamatzky;Georgios Ch. Sirakoulis
Year: 2022 | Volume: 69 | Issue: 10
Variability-Aware Approximate Circuit Synthesis via Genetic Optimization
Konstantinos Balaskas;Florian Klemme;Georgios Zervakis;Kostas Siozios;Hussam Amrouch;Jörg Henkel
Publication Year: 2022,Page(s):4141 - 4153
Cited by: Papers (2)
One of the major barriers that CMOS devices face at nanometer scale is increasing parameter variation due to manufacturing imperfections. Process variations severely inhibit the reliable operation of circuits, as the operational frequency at the nominal process corner is insufficient to suppress timing violations across the entire variability spectrum. To avoid variability-induced timing errors, p...Show More
A Synthesis-Analysis Machine With Self-Inspection Mechanism for Automatic Design of On-Chip Inductors Based on Artificial Neural Networks
Zhenyu Wang;Fuchen Yan;Shu Ma;Tao Yang;Huaizong Shao;Yong Wang
Publication Year: 2022,Page(s):4154 - 4167
Cited by: Papers (4)
An automatic inductor design process is helpful to reduce the design cycle of radio frequency (RF) integrated circuit (IC). This paper proposed an efficient synthesis-analysis machine (SAM) for on-chip inductor synthesis and modeling, as well as an automatic dataset generation (ADG) topology for the generation of artificial neural networks (ANNs) training dataset. The SAM consists of a synthesis A...Show More
Contact Information
Editor-in-Chief
Xinmiao Zhang
Associate Editor-in-Chief
The Ohio State University
Editor-in-Chief
Xuan 'Silvia' Zhang
Digital Communications Associate Editor-in-Chief
Northeastern University
Contact Information
Editor-in-Chief
Xinmiao Zhang
Associate Editor-in-Chief
The Ohio State University
Editor-in-Chief
Xuan 'Silvia' Zhang
Digital Communications Associate Editor-in-Chief
Northeastern University
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