Activity-Adaptive Architectures for Energy-Efficient Scalable Neural Recording Microsystems: A Review of Current and Future Directions

Wireless transmission of the recorded neural data without exceeding the extremely-limited available power is one of the most significant challenges in developing implantable brain neural interfaces, particularly for systems with higher channel count. Several generic and application-specific data reduction methods have been proposed in the literature with various levels of success in improving energy efficiency while preserving signal integrity. In this paper, we will review different approaches reported and will discuss their advantages and disadvantages. We will also discuss the opportunity that neural ADCs offer recently-reported in realizing an activity-dependent adaptive-resolution fully-dynamic-power neural recording architecture capable of near-loss-less data compression while reducing the required power for both recording and transmission.

I. Introduction

Neurological disorders affect more than one billion people worldwide today and the number is projected to increase with the world’s aging population [1]. Over the past decade, thanks to the advancements in the fields of neurotechnology and microelectronics, various implantable brain machine interfaces (BMI) have been developed to monitor, diagnose, and control different neurological events. A commonly agreed goal in the development of such technologies is increasing the number of sites that the device interacts with the living tissue (e.g., brain cells). Increasing the number of these "recording channels" allows for monitoring the brain neurological activity with a higher resolution, which enables more accurate detection of neurological events (e.g., an epilepsy seizure) as well as more effective control of these events through bio-feedback signals (e.g., electrical stimulation). However, considering these de-vices are either battery-powered or wirelessly-powered [2], [3], the overall energy budget is highly-constrained, preventing channel-count scaling beyond a certain limit. This motivates for identifying major energy consumers on these devices (i.e., bottlenecks for scaling) and improving their energy efficiency to be able to scale the number of channels without violating the overall power budget cap.