Investigating the relationship between electron mobility and velocity in deeply scaled NMOS via mechanical stress

The importance of low-field mobility to the performance of deep-sub-100-nm bulk MOSFETs is not well understood. In this work, we investigate experimentally how effective electron mobility at low lateral electric fields relates to velocity in the MOSFET saturation regime, where lateral fields in the channel are high. For short (L/sub eff//spl ap/45 nm) NMOS devices, mobility is modified by externally applying uniaxial stress and the corresponding shifts in electron velocity are found to be significant.

I. Introduction

For bulk MOSFETs it has been demonstrated that NMOS inversion-layer electron velocity near the source is not increasing with sub-100-nm scaling of channel length, and in fact may be decreasing slightly [1]. This may be due to degraded mobility in deeply-scaled bulk MOS, from the heavy channel doping required to suppress short-channel effects, and from ultra-thin gate oxide effects [2]. To better understand these scaling trends, as well as to assess potential benefits of technology alternatives for improved mobility (e.g., thin-film SOI, strained silicon) it is important to explore experimentally the relationship between low-field effective inversion-layer mobility and near-source electron velocity in aggressively scaled high-performance bulk NMOS devices operating in saturation . Previous experimental investigations [3], [4] of the relationship have employed silicon-on-insulator MOS structures with light-doped channels and gate oxides in the 4 nm (physical) range; the observed dependencies may not apply to deep-sub100-nm bulk NMOS devices with high channel doping. Experimental demonstrations of strained silicon technology [5], [6] suggest that low-field mobility is important to sub100-nm bulk MOSFET performance. However, in this case, differences in thermal properties, dopant diffusion, etc. (due to a different material system) complicate direct correlation of to performance.