High Performance Dual Gate Blue Laser Annealed Poly-Si Thin-Film Transistor for High-Resolution Displays

We report a dual gate (DG), low-temperature polysilicon (LTPS) thin-film transistor (TFT) using blue laser annealing (BLA) of amorphous silicon. The DG TFTs with variable bottom gate lengths (L_BG) from 2 to 8 μm and a fixed top gate length (L_TG) of 6 μm are investigated. The drain currents of the DG LTPS TFT with L_BG > L_TG by 2 μm under DG sweep (DS) are ~4.3 times those of the single gate TFT. The high carrier concentrations (~10¹⁹ cm^-3) at both interfaces (top gate insulator (GI)/poly-Si and poly-Si/bottom GI) under DS is confirmed by technology computer-aided design (TCAD) simulation, which might lead to high drain currents. The poly-Si layer exhibits no grain boundary protrusion from the transmission electron microscopy (TEM) cross-sectional micrograph and thus induces a strong bulk accumulation effect under DS. The fabricated DG TFT-based ring oscillator (RO) and shift register (SR) exhibit an excellent oscillation frequency of 15.8 MHz, fast-rising and falling time of 370 and 366 ns at a driving voltage of -10 V, respectively.

I. Introduction

The low-temperature poly-Si (LTPS) thin-film transistor (TFT) has been widely employed for liquid crystal display (LCD) and organic light-emitting diode (OLED) display due to its advantages of high field-effect mobility () and excellent electrical stability [1]–[5]. Extensive research has been performed on LTPS as a semiconducting material with various crystallization methods to achieve high-performance TFTs such as excimer laser annealing (ELA) [6]–[8], solid-phase crystallization [9], [10], and continuous-wave green laser annealing [11], [12]. Although ELALTPS has several drawbacks such as grain size variation and poor performance uniformity, it is widely implemented for small-size, high-resolution displays. Besides, the conventional ELA method used for display manufacturing has the limitation of having a small grain size that limits on-current (), and the existence of grain boundary (GB) protrusion [13]. To overcome these issues, the ELA TFTs with a dual gate (DG) structure and a sequential lateral solidification (SLS) method are introduced [14], [15]. By implementing DG TFT structure under DG sweep (DS), the can be enhanced approximately two times as compared to a single gate (SG) TFT [16]–[20].