Gate-All-Around Charge Plasma-Based Dual Material Gate-Stack Nanowire FET for Enhanced Analog Performance

In this paper, a gate-all-around (GAA) charge plasma-based dopingless dual material gate nanowire FET is proposed (CP-DM). This structure is further explored by adding gate-stack (high-k + SiO2) feature (CP-GS-DM). In these dopingless structures, source/drain is induced using a charge plasma concept by an appropriate selection of work functions for source/drain electrodes. The dopingless devices offer low thermal budget with easier fabrication steps and reduced random dopant fluctuations effect. Both the dopingless structures are investigated for analog performance, and results are compared with those obtained from the GAA junctionless dual material (JL-DM) gate and the JL gate-stacked DM gate (JL-GS-DM), respectively. The charge plasma-based dopingless devices when compared with their JL counterpart show improvement in drive current (I_D), transconductance (g_m), transconductance gain factor (g_m/I_D), output conductance (g_ds), early voltage (V_AE), intrinsic gain (A_v), drain-induced barrier lowering, and subthreshold slope. Thus, dopingless structures show enhanced analog performance with reduced short channel effects. The charge plasma based dopingless gate stacked dual material gate (CP-GS-DM) shows the best performance of all the structures. The analysis is further carried out for investigating the device design parameters effect on performance, namely, total gate length, L_G, and ratio of control gate length to total gate length, L_M1/L_G. This way dopingless charge plasma-based devices incorporate DM and GS features that make these devices interesting and reliable candidatesfor analog applicationwith cost-effective fabrication.

I. Introduction

Among various multigate approaches, a gate-all-around (GAA) silicon nanowire MOSFET (NWFET) has captured the attention of many research groups around the world. This is due to the outstanding capability of GAA NWFET for continuous scaling down the size of the devices, because it provides the best electrostatic control, higher packaging density, and short channel effects (SCEs) immunity [1]–[4]. In spite of many benefits, GAA NWFETs also suffer from a problem of high series resistance which originates from the formation of sharp junctions between highly doped source/drain and partially doped channel [5], [6]. A solution for this problem is a structure without having physical junctions and termed a junctionless (JL) NWFET [7]–[9]. JL NWFETs are made of heavily doped regions of source, channel, and drain. Due to very high doping concentration, JL devices encounter many problems such as low caused by a reduction in carrier mobility [10] and low [9]–[11]. JL NWFETs bear elevated sensitivity toward radom dopant fluctuations (RDFs) because of heavy doping [12], [13]. A device named a charge plasma-based dopingless FET resolves these problems of JL devices. The charge plasma concept is proposed by Hueting et al. [14]. By eliminating the need of doping, this technique resolves the problems of doping control [15]. This charge plasma concept for dopingless device designing is applied to bipolar transistors [16], tunnel FET [17]–[19], MOSFET [20], and GAA NWFET [21]. This concept offers low thermal budget, enhanced , and lower SCEs. It also shows superior immunity toward variations caused by RDFs as compared to that of JL devices [20].