Z-Directed Component (ZDC) Technology for Power Integrity Applications

An important aspect of ensuring the power integrity of a power distribution network (PDN) design is to determine the layout, value, package size, and number of decoupling capacitors. To solve the limitation of the vertical connection of the surface-mounting-type capacitor to the power net area fill, a new concept of a capacitor denoted the Z-directed component (ZDC) is proposed in this paper. There are many applications possible with the ZDC with the first implementation as a decoupling capacitor. The ZDC capacitors can be integrated within the printed circuit board (PCB) substrate directly below the package ball and eliminate the integrated circuit (IC) to decoupling capacitor horizontal distance across the power net area fill. Furthermore, the inductance associated with the vertical current paths on the vias from the IC package to the horizontal power net area fill and similarly for the surface-mounted technology decoupling capacitors is eliminated. Since only the inductance of the ZDC capacitor itself remains, there is the possibility of using far fewer capacitors to achieve a high-frequency target impedance specification. The ZDC is a promising technology that gives the PCB designer the opportunity to integrate low equivalent series inductance decoupling capacitors much closer to the noise source than traditional surface-mount capacitors. In addition, in this paper, a high-order model is introduced for the ZDC capacitor to better understand the high-frequency characteristics of the component and is verified with measurements.

I. Introduction

Today's high-speed digital and communications electronics are operating at higher and higher frequencies, and the design density is also increasing. Multiple levels of a power distribution network (PDN) design are used to meet the requirements to limit the voltage noise in the system. The system PDN includes decoupling capacitors on the printed circuit board (PCB), the PCB parallel plane power net area fill, as well as package and on-chip PDN. The state-of-the-art PCB PDN design involves multilayer structures and a large number of surface-mounted decoupling capacitors on the top of the PCB, on the bottom of the PCB away from the integrated circuit (IC) region, and on the bottom layer under the IC, as shown in Fig. 1(a) [1], [2]. Fig. 1.

(a) Generic PCB PDN geometry for SMT components. (b) ZDC implementation in the PCB.