Zero-Power Feed-Forward Spur Cancelation for Supply-Regulated CMOS Ring PLLs

A new reference-spur cancelation technique is presented for supply-regulated ring-oscillator-based integer-N phaselocked loops (PLLs). A passive RC filter is used to implement a feed-forward (FF) spur-coupling path to perform spur cancelation at the PLL control signal. The proposed technique achieves a simulated spur cancelation of about 22 dB at the first spur harmonic. The simulated postcancelation spur value is -79 dBc for an oscillator gain of 0.1 GHz/V and -46 dBc for an oscillator gain of 6 GHz/V. Spur cancelation is also robust against large process, voltage, and temperature variations in the gain and bandwidth of the FF path. A 1-GHz integerN PLL prototype in a 65-nm CMOS process has a measured cancelation of 19.5 and 13 dB at the first and the second spur harmonic, respectively, with 320 μW of total power consumption. The PLL prototype has an oscillator gain of 1.5 GHz/V, which results in a postcancelation spur of -53 dBc. The proposed zero-power technique is suitable for low-power PLLs as it achieves a large spur cancelation without requiring any additional power consumption or calibration.

I. Introduction

More than 20 billion low-cost consumer devices are envisioned to have low data-rate wireless connectivity by 2020 [1] for monitoring, diagnostics, and corrections [2], i.e., a global expansion of the Internet of Things. The subgigahertz bands in the industrial, scientific, and medical category (e.g., 915 MHz in USA and 920 MHz in Japan) are an attractive choice for these low-rate applications using low-power communication standards, such as IEEE 802.15.4 [3].