A quad-core 28–32 GHz transmit/receive 5G phased-array IC with flip-chip packaging in SiGe BiCMOS

This work presents a quad-core 28-32 GHz transmit/receive phased-array integrated circuit (IC) with flipchip packaging for 5G communication links. The IC consists of 4 Tx/Rx channels each with 6-bit phase and 14 dB amplitude control. The noise figure in the RX mode is 4.6 dB, the lowest reported to date to our best knowledge, and the output power in transmit mode is 10 dBm at P1dB. The power consumption is 105 mW and 200 mW in the RX and TX modes respectively, per channel. The chip is flipped on a low cost RF board with a 2×2 antenna array for a range of system-level measurements. The array has a measured EIRP of 24.5 dBm, and is used in a 1 meter communication link achieving 64-QAM 2.4 Gbps data rate with an EVM of 2.89%.

I. Introduction

The Federal Communications Commission recently approved the use of 28, 39 and 60 GHz bands for use in next generation 5G systems. High data rates at these bands are to be achieved using 2-dimensional phased arrays at both the base-stations and hand-held units for directive beamforming capable of scanning in both planes [1]–[3]. The goal of this work is to develop a high performance quad-core phased-array chip at 28 GHz and to prove using a set of system-level measurements that it can be used in large-scale phased-arrays for 5G links.