Simulation of Dual spacer Double gate Junction less Transistor

Now a days different Junction less Transistor (JLT) structures proposed which includes silicon on insulator(SOI) JLT, Double gate (DGLJT) JLT, Bulk planar JLT, Gate all around (GAA) JLT etc. to improve performance parameters such as sub threshold slope (SS), off state leakage current, drain induced barrier lowering (DIBL) etc. In this paper, JLTs with dual spacer structures shows better improvement as compared to single spacer structure. Due to high electron mobility property of GaAs, Si has been replace by it as channel material in device. It has been also seen that there is off state current reduction while increment in on state current.

I. Introduction

Recently, In semiconductor industry scaling of device takes more attention to improve density of integrated circuits [1]. For that requirement different novel device structures have been reported such as junction less transistors (JLT) [2],tunnel field effect transistor(TFET)[3] etc. Due to the presence of junction less path from source to drain JLTs shows lower short channel effects(SCE). Junction less transistors gives better improvement in performance parameters as compared to conventional MOSFET[4]for low power applications. Various device structures such as double-gate JLT[5],bulk planar(BP)[6] and silicon on insulator(SOI)[7], [19],JLT with spacer[8], [20] have been reported to reduced off state leakage current.