Clocked Adiabatic XOR and XNOR CMOS Gates Design Based on Graphene Nanoribbon Complementary Field Effect Transistors

In this paper, graphene nanoribbon field effect transistors (GNR FET) have been used in design of new energy-efficient XNOR/XOR gates based on clocked adiabatic logic (CAL), which results in the reduction of power density by nearly 65% comparing with the earlier CAL design in 45 nm technology node. In addition, the GNR FET allows scaling of supply voltage, which results in nearly three times reduction in power density. The on-chip power density of new XNOR/XOR gates remains below the limit reported by the International Technology Roadmap for Semiconductors (ITRS) up to the operation frequency of about 1GHz at the scaled supply voltage equal to 0.7V.

I. Introduction

Although aggressive scaling of transistor dimensions and increasing chip complexity has satisfied the demand for increasing the performance of integrated circuits, reducing the power dissipation has been always a major research effort for applications in portable devices. At the device level, the reduction in power dissipation has been achieved mainly by scaling down the supply voltage and reducing capacitances with the scaling of transistors and interconnects. However, transistor and interconnect dimensions are limited in size due to physics behind it. Furthermore, small geometry effects in MOS FETs [1] playa major role in the performance of integrated circuits as it increases the leakage current and consequently the static power dissipation. The well-known Moore's law is nearly approaching to an end in next decade, there is increasing efforts in search of new materials such as carbon nanotubes (CNT) [2] and graphene [1], [3] possibly substituting silicon in integrated circuits. ITRS has predicted that the higher carrier mobilities in these materials allow more aggressive supply voltage scaling at the same time with higher drive current than in silicon MOSFETs, resulting in improvement in both speed and power dissipation [4]. Graphene is a promising alternative to silicon due to its atomically thin planar structure, high carrier concentration, high carrier mobilities and thermal conductivity [5]. Patterning narrow stripes of graphene known as graphene nanoribbons (GNR) can open a band gap of several hundred meV due to the quantum confinement of carriers [6] in order to make GNR field effect transistor suitable for logic applications. At the circuit level, the reduction in energy loss or heat dissipation can be obtained in energy recovery techniques [7] using the two key rules of clocked adiabatic logic: Never tum-on a transistor when there is a potential difference across it, and never turn-off a transistor when current is flowing through it. Novel GNR FET-based circuits can be desired for ultra-low energy operation.