I. Introduction
Due to the higher frequency of operation of modern integrated circuits (ICs), accurate de-embedding techniques are even more important in every phase of the IC design, starting from the device characterization to the package modeling. The device characterization requires deembedding techniques both for on-die and on-package measurements. This techniques are generally developed for a reduced number of ports, typically four-port structure. In [1] a four-port calibration technique has been developed, for “on-wafer” measurements, using admittance matrices. A de-embedding methodology for on-wafer multi-port device characterization, based on the trasmission-line theory and the use of shield-based test structures, has been proposed in [2]. In [3] a circuit based four-port de-embedding technique is set up to model the parasitic effects of the package in power MOSFETs, used in RF applications.