A novel dynamic element matching technique suited for high pass ΔΣ ADCs

This paper presents a novel dynamic element matching technique (DEM) suited for high pass (HP) Delta Sigma (ΔΣ) modulators. It is based on transforming the high pass filtering behavior of classical DEM algorithms into a low pass behavior to make them adapted for HP ΔΣ modulators. The proposed technique is demonstrated for the data weight averaging (DWA) algorithm at the system level and the electrical level using a 65 nm CMOS process. The achieved performances in terms of SFDR and SNDR are similar to the performances of classical low pass (LP) ΔΣ modulators employing regular DWA. Moreover the required additional complexity is very low : just 8 simple switches and some digital gates.

I. Introduction

With the scaling down of technology, analog to digital converters (ADCs) are becoming best candidates for audio and radio digitization [1]. From one technology node to the following, their digital part gains a factor two of speed and area and even more in terms of power consumption. As for the analog, the benefits are mainly in terms of speed which is allowing to extend their conversion bandwidth up to several tenths of MHz [2].