Interface Trap Density of Gate-All-Around Silicon Nanowire Field-Effect Transistors With TiN Gate: Extraction and Compact Model

Si/SiO₂ interface trap charge distribution of cylindrical cross-sectioned gate-all-around silicon nanowire field-effect transistor is extracted by using three-dimensional simulation. While the interface chemistry of conventional gatestack ( Si/SiO₂ polysilicon) in conventional planar devices is well documented, not much work is available on interface trap distribution Dit of alternate gatestacks (gatestacks employing alternate gate materials) in silicon nanowire MOSFET devices. Furthermore, a compact drain current model with interface trap charge parameter is presented. The model is based on gradual channel approximation and uses self-consistent calculation of interface trap charge and surface potential to reproduce experimental current-voltage characteristics.

I. Introduction

With constant need for scaling, alternate 3-D structures and materials are being tested. Gate-all-around (GAA) devices are expected to play a major role in sustaining Moore's law [1]. These 3-D devices show better immunity to short channel effects (SCEs) compared with conventional planar mosfet devices. However, the reported experimental subthreshold swing (SS) values for long-channel GAA silicon nanowire field-effect transistors (SNWFETs) are found to be much beyond the ideal value of 60 mV/dec. It is a well known fact that in the absence of SCEs, the interface trap states are responsible for SS degradation.