I. Introduction
Silicon-based phased arrays have now been demonstrated from X-band to V-band using RF beam-forming techniques [1]– [7]. The main advantages of the RF architecture are its simplicity, system-level linearity, low power consumption (no LO drivers, no LO distribution), and the use of a single high-performance transceiver. Most of the published work presents on-chip measurements using CPW probes, but this ignores the packaging aspects of multi-element phased arrays, such as RF transitions and associated impedance matching networks, coupling between the different RF ports, V cc de-coupling and oscillations–especially in high gain designs, and the creation of a low-inductance ground between the chip and the antenna distribution board. These issues if not properly designed and mitigated, can degrade the phased-array chip performance and render it un-usable in practical implementations. Functional block diagram of the 8-element silicon phased array chip (from 1 D. (a) The 8-element X/Ku-band phased array with the silicon chip at its center, and (b) input and output transmission lines around the silicon chip ().