A 24-GHz phased-array receiver in 0.13-µm CMOS using an 8-GHz LO

This paper presents a 24-GHz two-channel phased-array receiver. The receiver adopts the LO-phase-shifting approach and employs a sub-harmonically injection-locked phase-shifter. A CMOS-only prototype, fabricated in a 130-nm SiGe BiCMOS technology, draws 16-mA of current from a 1.5-V supply and consists of a injection-locked oscillator (operating as a phase-shifter, LO-buffer and frequency multiplier), a down-conversion mixer and an IF-buffer. The worst-case measured amplitude and phase errors are 1.5-dB and 4°. The two-channel receiver occupies an active area of 0.23-mm².

I. Introduction

To meet the ever-increasing demands for higher data-rates in wireless communication, modern wireless standards are moving to multi-antenna architectures. There is renewed interest in operating at the millimeter frequencies as the congestion at the lower ISM bands are increasing. Commercial systems prefer silicon-based technologies (CMOS/BiCMOS) for cost-related advantages and integration levels. With improvements in technology, silicon is rapidly closing its frequency gap with III-V technologies. Modern 65-nm CMOS and 130-nm BiCMOS processes offer beyond 200-GHz. This has led to extensive research in building silicon-based solutions for mm-wave commercial and defense applications [1]–[5]. Millimeter frequencies of commercial interest include 24GHz (for automotive radar and wireless communication), 60GHz (for wireless communication), 77 GHz (for automotive radar) and certain sub-bands in the W-band (for passive imaging).