Fabrication and Characterization of Gate-All-Around Silicon Nanowires on Bulk Silicon

This paper reports on the top-down fabrication and electrical performance of silicon nanowire (SiNW) gate-all-around (GAA) n-type and p-type MOSFET devices integrated on bulk silicon using a local-silicon-on-insulator (SOI) process. The proposed local-SOI fabrication provides various nanowire cross sections: Omega-like, pentagonal, triangular, and circular, all controlled by isotropic etching using nitride spacers and silicon sacrificial oxidation. The reported top-down SiNW fabrication offers excellent control of wire doping and placement, as well as ohmic source and drain contacts. A particular feature of the process is the buildup of a tensile strain in all suspended nanowires, attaining values of few percents, reflected in stress values higher than 2-3 GPa. A very high yield (>90%) is obtained in terms of functionality of long-channel SiNW GAA mosfet. Device characteristics are reported from cryogenic temperature (T = 5 K) up to 150 ^degC, and promising characteristics in terms of low-field electron mobility, threshold voltage control, and subthreshold slope are demonstrated. Low field mobility for electrons up to 850 cm² /Vmiddots is reported at room temperature in suspended devices with triangular cross sections; this mobility enhancement is explained by the process-induced tensile strain. In short, suspended SiNW GAA with small triangular cross sections, a single-electron transistor (SET) operation regime is highlighted at T = 5 K. This is attributed to a combined effect of strain and corner conduction in triangular channel cross sections, suggesting the possibility to hybridize CMOS and SET functions by a unique nanowire fabrication platform.

I. Introduction

Scaling of silicon MOS devices has historically been driven by the ambition to improve the device performances (such as speed) and decrease their cost by increasing the integration density. When scaling the mosfet into the sub-100-nm gate length domain, the bulk-silicon transistor is facing serious problems concerning the control of short-channel effects (SCEs) and maintaining the traditional Dennard's scaling rules [1], and new solutions like multiple-gate mosfet on silicon-on-insulator (SOI) substrates should be considered [2]. The quasi-ideal transistor architecture to address the end-of-the-roadmap of scaling is today considered a semiconductor nanowire with a wrapped gate stack. The purpose of this paper is to describe a possible top-down fabrication of gate-all-around (GAA) mosfet architectures on bulk silicon (see Fig. 1) and some of their basic electrical characteristics. Fig. 1.

(a) Top view layout of an n-type GAA-mosfet with a cut through the channel. (b) SEM cross section view of a triangular GAA-mosfet with dimensions. (c) Schematic 3-D view of a GAA-mosfet on bulk silicon. A deposited LPCVD oxide layer (LTO) serves as buried oxide.