Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories

The fabrication of crossbar memories with sublithographic features is expected to be feasible within several emerging technologies; in all of them, the nanowire (NW) decoder is a critical part since it bridges the sublithographic wires to the outer circuitry that is defined on the lithography scale. In this paper, we evaluate the addressing scheme of the decoder circuit for NW crossbar arrays, based on the existing technological solutions for threshold voltage differentiation of NW devices. This is equivalent to using a multivalued logic addressing scheme. With this approach, it is possible to reduce the decoder size and keep it defect tolerant. We formally define two types of multivalued codes (i.e., hot and reflexive codes), and we estimate their yield under high variability conditions. Multivalued hot decoders yield better area saving than n-ary reflexive codes, and under severe conditions, reflexive codes enable a nonvanishing part of the code space to randomly recover. The choice of the optimal combination of decoder type and logic level saves area up to 24%. We also show that the precision of the addressing voltages when a high variability affects the threshold voltages is a crucial parameter for the decoder design and permits large savings in memory area. Moreover, a precise knowledge about the variability level improves the design of memory decoders by giving the right optimal code.

I. Introduction

The trend toward deeply scaled evolutionary and emerging technologies, as predicted by the International Technology Roadmap for Semiconductors [1], and the corresponding increase in variability and defect rates of devices and interconnect justifies the reintroduction of regular architectures. Within this design style, sometimes referred to as array logic, switching devices [molecular switches and semiconducting nanowires (NWs)] can be fabricated and deposited into highly dense regular arrays, called crossbar arrays. A specific example is given by two perpendicular strips of parallel NWs storing the information or executing the computation at the matrix nodes (i.e., at the NW crosspoints) [5].