A Novel Voltage Scaling Algorithm through Ant Colony Optimization for Embedded Distributed Systems

Dynamic voltage scaling, supported by many DVS-enabled processors, is an efficient technique for energy-efficient embedded systems. Many researchers work on DVS and have presented various DVS algorithms, some with quite good results. However, the previous algorithms either have a large time complexity or obtain results sensitive to the count of the voltage modes. Fine-grained voltage modes lead to optimal results, but coarse-grained voltage modes cause less optimal one. This paper presents a new algorithm based on ant colony optimization, called ant colony optimization voltage and task scheduling (ACO-VTS) with a low time complexity implemented by parallelizing and its linear time approximation algorithm. Both of them generate quite good results, saving up to 30% more energy than one of the previous ones under coarse-grained modes, but their results don't depend on the number of modes available.

1. Introduction

Moore's law has driven the transistor density of VLSI doubled every 18 months for almost 40 years, which makes power consumption the major challenging problem for VLSI and computing systems containing VLSI components. Researchers studied the problem in depth and invented a lot of solutions for the problem, including many low-power techniques at various levels.