I. Introduction
The three-level-inverter topology offers reduced harmonic distortion of the output current and low-voltage stress of the semiconductor switches [1]. It enables operation at very low switching frequency and hence is a preferred solution for high-power medium-voltage applications. Of particular interest is the neutral point clamped (NPC) topology [2], the circuit diagram of which is shown in Fig. 1.
Circuit diagram of a three-level inverter, npc topology.