LASER Anneal to Enable Ultimate CMOS Scaling with PMOS Band Edge Metal Gate/High-K Stacks

For the first time, we report on the beneficial result for minimizing the activation thermal budget using LASER anneals with metal-oxide-gate-electrode/high-k dielectric MOSFETs. With LASER activation, EOT for PMOS conductive metal-oxide gated devices is reduced 4-5Aring compared to conventional RTP activation methods leading to more aggressive ultimate CMOS scaling when using a conductive metal-oxide for the PMOS gate electrode

I. Introduction

Current technology roadmaps for ultra-scaled metal-oxide-semiconductor field-effect transistor (MOSFET) devices indicate that continued deep sub-micron device scaling now requires gate dielectrics to be thinned to much less than 1.5 nm EOT. However, the current technology, using materials of poly-silicon gate electrodes and silicon dioxide or oxynitride gate dielectrics, can not deliver the desired device performance for this ultra-scaled gate-dielectric thickness. To overcome this problem, extensive studies are underway investigating both metal-gate electrodes to replace poly-silicon gates and eliminate depletion effects, and high dielectric constant (high-K) metal-oxide insulators to allow for continued electrical thickness scaling with a physically thicker gate dielectric. Along with identifying the correct materials, the gate-stack device fabrication process and accompanying thermal budgets which can achieve the required device scaling must also be determined. Here we report on results related to the device fabrication process thermal budget using metal-gate electrodes and high-K gate dielectrics. Furthermore, we report here for the first time the effects of ultra-short time laser activation anneals with metal-gate high-K stacks.