An embedding debugging architecture for SOCs

Multiple cores embedded debugging architecture for system on chip design (SOC) is presented. It presents an asymmetrical functional test problem. To analyze the problem and optimize performance in multicore operation, debug tools with interfaces are exercised for several cores. HyperJTAG (joint test action group) interface reduces the IO pin interfaces required for debugging several cores. To overcome the wiring problem in hyperJTAG, wire routing and debugging synchronization is proposed. Hyper debug action nodes at each core initiate global or local control actions that synchronously reset the cores. To provide a virtual connection between the processor core in the SoC and its corresponding probe control, MED (multicore embedded debugging) software tool is proposed. This allows a contiguous analysis flow from the system level simulation models of SoC systems through FPGA and emulation prototyping and finally it debug the silicon hardware.

1) The Debugging Evolution

Looking at Fig. 3, we see a steady increase in the difficulty—as defined by the ratio of gates vs. available pins—in pulling design information off the chip. This rise largely tracks and reflects the changes in design architectures and chip capabilities. The emerging trend towards SoC devices is no different. Fig. 3

SoC debug evolution