Modeling of tunneling current and gate dielectric reliability for nonvolatile memory devices

We present a hierarchy of tunneling models suitable for the two- and three-dimensional simulation of logic and nonvolatile semiconductor memory devices. The crucial modeling topics are comprehensively discussed, namely, the modeling of the energy distribution function in the channel to account for hot-carrier tunneling, the calculation of the transmission coefficient of single and layered dielectrics, the influence of quasi-bound states in the inversion layer, the modeling of static and transient defect-assisted tunneling, and the modeling of dielectric degradation and breakdown. We propose a set of models to link the gate leakage to the creation of traps in the dielectric layer, the threshold voltage shift, and eventual dielectric breakdown. The simulation results are compared to commonly used compact models and measurements of logic and nonvolatile memory devices.

I. Introduction

For the prediction of performance and for the optimization of nonvolatile memory devices, accurate simulation of quantum-mechanical tunneling effects has always been of paramount interest [1]. The application area of tunneling models ranges from the prediction of gate leakage in MOS transistors, the evaluation of gate stacks for advanced high- gate insulator materials, and the optimization of programming and erasing times in nonvolatile semiconductor memory cells, to the study of source-drain tunneling. Fig. 1. Tunneling processes in a MOS structure. Direct tunneling processes (ECB, EVB, and HVB) are covered in Section II, while Section III deals with TAT transitions. Bound and quasi-bound states are studied in Section II.C.