I. Introduction
Exceptional effort is focused on extending the data rate capabilities of economical copper backplanes. While VLSI circuit speed is steadily increasing, the wires between chips and even on-chip are becoming bottlenecks [1] [2]. To avoid costly optical interconnects, circuit designers are forced to equalize the channel to increase the data rate, implement alternative channel coding schemes, or simply use more parallel channels [3] [4]. Ultimately, space and power dissipation limits the number of parallel channels.