A Digital Pre-Distortion Technique for High-Linearity, Low-Power, Compact, Phase Interpolators

The linearity of phase interpolators (PIs) is enhanced by pre-distorting the PI control weights, instead of increasing the number of clock phases. This approach shifts the design complexity from the analog to the digital domain, resulting in a PI with high linearity, low power consumption, low clock jitter, compact area. The optimized pre-distorted control weights effectively suppress the phase nonlinearity stemming from deterministic sources across PVT corners. Post-layout simulation results demonstrate that a 65-nm implementation of a 7-bit PI with 4-phase input has a peak-to-peak integral nonlinearity better than 1.6 LSB across PVT corners and under circuit mismatch at 7 GHz, with a power consumption of 4.0 mW, and a circuit area of 0.0085 mm². This performance is competitive with more complex PI designs.

I. Introduction

The ever-growing demand for high data throughput in cutting-edge applications like high-performance computing is driving a relentless push for increased data link bandwidth [1]. This escalating need for data bandwidth requires the use of high-speed, precise clocking circuits in Serializer/Deserializer (SerDes) circuits. Integrating multiple SerDes on System-on-Chips fabricated in advanced technology nodes introduces more stringent design constraints for power consumption and area.