On-Chip Emulation and Measurement of Variable-Length Photocurrents in Sub-50nm ICs

This article presents a circuit design for measuring and emulating radiation-induced photocurrent pulses in dense, highly scaled integrated circuits (ICs) and experimental results from an implementation in a 45-nm partially depleted silicon-on-insulator (PD-SOI) process. This photocurrent measurement circuit (PMC) expands upon other work by introducing new capabilities and measurement procedures, including a method for capturing arbitrarily long pulses and an arbitrary-waveform generator (AWG) that enables flexible built-in self-test (BIST) capabilities as well as emulation of transient radiation events. Experimental PMC measurements of currents generated by flash X-ray irradiation, pulsed-laser irradiation, and AWG emulation show excellent agreement and are corroborated by technology computer-aided design (TCAD) simulations; in particular, AWG recreations of experimental flash X-ray photocurrent responses match the original data with as little as 1.375% mean absolute percentage error (MAPE). Comparisons of different transistor structures also indicate a relatively insignificant photocurrent response in body-tied devices, suggesting that floating body effects are a dominant factor for this process. Holistically, these results demonstrate the efficacy of the PMC.

I. Introduction

Transient photocurrent generated in diodes and transistors is one of the earliest topics of radiation-effects study [1], [2], and photocurrent characterization procedures have changed very little since their conception. These traditional techniques have been instrumental in the development of most transient-photocurrent models and equations in use today [3], [4], [5], [6], [7], [8], [9] and are still viable for discrete components and older technology nodes; unfortunately, characterizing photocurrent effects in contemporary integrated circuits (ICs) is not as simple. As transistors have scaled down in size in accordance with Moore’s law [10], so too have their sensitive regions and photocurrent responses [11]. This scaling trend can be augmented by certain semiconductor wafer technologies, such as the silicon-on-insulator (SOI) technology used for the designs presented in this work. In SOI, the active silicon is isolated from the substrate by a buried oxide (BOX) layer, which shrinks the sensitive region further and typically results in a significantly smaller primary photocurrent response [4], [12], [13], [14], [15]. In contemporary sub-50nm SOI processes, the photocurrent response is often dwarfed by leakage currents and can be indistinguishable from measurement noise.