I. Introduction
Today's data center power management is extremely challenging: the massive introduction of artificial intelligence in cloud computing requires the adoption of processors and ASICs [1] as specialized hardware accelerators. These devices are typically developed with short-channel technology, require low input supply voltage (i.e., 0.8 V) and may need very high currents (up to 1 kA). This low regulated voltage, together with the high current requirement, makes the Voltage Regulator Module (VRM) design very challenging, involving careful layout design and Power Distribution Network (PDN) shaping to maintain the voltage regulated during the strong load transients. In order to simplify the VRM design effort, reduce the number of power pins, and better regulate the core voltage, Intel processors integrate voltage regulator modules (FIVR) on-chip [2], [3]; however, this is not the case for generic ASICs used as hardware accelerators. It is necessary to underline that the reduction of the load transient effect by a reduction of ) allows a potential energy saving since the regulation supply voltage of the digital load can be shifted close to the tolerable lower limit.