I. Introduction
Design and optimization for power distribution networks (PDNs) are critical for the state-of-the-art applications, such as laptops and smartphones. The PDN is designed to maintain a constant supply voltage for the chips and keep it within a narrow tolerance band [1], [2], [3]. The demand for low-voltage operation of a high-speed digital interface is increasing due to the faster logic transition [4], [5]; however, the noise margin is also compromised. Evaluating the fluctuation of the power rail voltage under different loading conditions is increasingly important.