A Sub-Picosecond Resolution 0.5–1.5 GHz Digital-to-Phase Converter

A digital-to-phase converter (DPC) is an essential building block in applications such as source-synchronous interfaces and digital phase modulators. The resolution of DPCs using analog phase interpolators is severely affected by the operating frequency and rise times of the interpolator inputs. In this paper, we present a new DPC architecture that achieves high resolution independent of both the operating frequency and the rise time. The 8 phases generated by a phase-locked loop are dithered using a delta-sigma modulator to shape the truncation error to high frequency and is subsequently filtered using a delay-locked loop phase filter. The test chip, fabricated in a 0.13 mum CMOS process, operates from 0.5 -1.5 GHz and achieves a differential nonlinearity of less than plusmn0.1 ps and an integral nonlinearity of plusmn12 ps. The total power consumption while operating at 1 GHz is 15 mW.

I. Introduction

Source-Synchronous interfaces are a class of point-to-point links that are widely used in microprocessor-memory interfaces and communication switches. A simplified block diagram of a typical source-synchronous interface is shown in Fig. 1. in this system, a clock is transmitted along with the data on a separate dedicated channel to the receiver. the clock channel is typically shared among multiple data channels and clock edges are synchronized with the data transitions at the transmitter. If the data and clock transmission lines are perfectly matched, the time of flight of the data and the clock are equal, and as a result, clock and data remain synchronized at the receiver as well. However, as data rates increase to the multi-gigabit-per-second range, it is uneconomical to match the time of flight of clock and data paths to picosecond accuracy. This mismatch results in a skew between the clock and data at the receiver causing sub-optimal sampling of the incoming data. One can improve the timing margin by reducing the skew between the received clock and data by using a method to introduce a controlled phase shift on the clock. the focus of this paper is the implementation of circuits that provide a means to introduce such a programmable phase shift. A digital-to-phase converter (DPC) is a circuit block that is often used to introduce a phase shift whose amount is controlled by an input digital word . It is important to note that the resolution of the DPC is of paramount importance as this determines the residual skew between the clock and data, which in turn directly affects the bit error rate (BER) of the link. This paper presents the design and experimental results of a DPC that utilizes delta-sigma modulation and phase filtering to achieve resolution much higher than what is achievable with traditional digital phase interpolators. Even though the design of the DPC is presented in the context of source-synchronous interfaces, it is worth mentioning that there are several other applications for DPCs in measurement instrumentation and the techniques developed here can directly be used in those applications. Fig. 1.

Typical source-synchronous interface.