Improving Linearity in CMOS Phase Interpolators

We compare the prior art in phase interpolators (PIs), classifying them as current-mode, voltage-mode, and integrating-mode PI. Next, we present an integrating-mode PI where the voltage slopes with high phase linearity are generated through the integration of phase-shifted weighted current sources. The constant and variable voltage slopes are generated by current sources/sinks created using stacked devices in a 0.75-V 5-nm finFET technology. This PI technique supports the high-speed and low-power operation and achieves dual-edge interpolation with improved duty-cycle distortion characteristics. The PI generates an output clock with 9 bits of resolution and a small peak-to-peak integral nonlinearity (INLpp) and peak-to-peak differential nonlinearity (DNLpp) of 2.4° and 1.4°, respectively, at 13.3 GHz with just quadrature clock inputs. The PI has a 71-fsrms random jitter (integrated from 3 MHz to 3 GHz) and occupies an active area of 0.006 mm2 while consuming 6-mW power at 14 GHz. An integrated rotation spur of −42.6 dBc for 256-ppm modulation at 13.3-GHz operating frequency is achieved for 1-GHz update rate for the dynamic linearity measurements.

I. Introduction

Fast-growing data traffic in data centers demands the wireline transceivers to operate at higher data rates. A multilane transceiver implementation is required to support high data rates necessitating low-power and compact clocking. The CMOS technology scaling also helps advanced nodes [1], [2] provide fast-switching transistors. However, the reduced supply voltage which accompanies node scaling favors digital-friendly techniques, and consequently, clocking solutions using current-mode logic (CML) [3] are unamenable.