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Showing 1-25 of 621 resultsfor "Index Terms":delay-locked loop (DLL)
"Index Terms":delay-locked loop (DLL)
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A Programmable Edge-Combining DLL With a Current-Splitting Charge Pump for Spur Suppression
A programmable edge-combining delay-locked loop (DLL) with fast switching transient and reduced output spur is presented in this work. With 12 delay cells adopted in the DLL, the programmable frequency-multiplied output can be quickly switched between ×6, ×3, and ×2 without affecting the lock state of the DLL. Output spur is suppressed by reducing the DLL phase offset in th...Show More
An Implementation of Fast-Locking and Wide-Range 11-bit Reversible SAR DLL
This brief proposes a novel circuit architecture of an 11-bit reversible successive approximation register (RSAR)-controlled all-digital delay-locked loop (DLL), which could achieve adaptive bandwidth in a wide operation range by utilizing the modified binary search algorithm of the RSAR scheme. Moreover, it is fast locking because it finds the suitable delay range first and the successive approxi...Show More
A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction
A low phase noise, delay-locked loop-based programmable frequency multiplier, with the multiplication ratio from 13 to 20 and output frequency range from 900 MHz to 2.9 GHz, is reported in this brief. A new switching control scheme is employed in the circuit to enable the capability of locking to frequencies either above or below the start-up frequency without initialization. To reduce the spuriou...Show More
A Multiphase DLL With a Novel Fast-Locking Fine-Code Time-to-Digital Converter
Dandan Zhang;Hai-Gang Yang;Wenrui Zhu;Wei Li;Zhihong Huang;Lin Li;Tianyi Li
This brief presents a fast-locking multiphase closed-loop delay-locked loop (DLL). The proposed DLL employs a novel rapid-tracking time-to-digital converter that spends only two clock cycles to generate fine codes. This greatly reduces the fine-locking time and hence the total locking time that goes down to eight input reference clock cycles, shortened by 80%-95% compared with previous...Show More
A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With 4\times Oversampling
In this brief, a delay-locked loop (DLL)-based burst-mode clock and data recovery (BMCDR) circuit using a 4× oversampling technique is realized for passive optical network. With the help of DLL to track the input phase, the proposed circuit can recover the burstmode data in a short acquisition time and achieve large jitter tolerance. In addition, a 2.5-GHz four-phase clock generator is...Show More
A semi-digital delay-locked loop using an analog-based finite state machine
This brief describes a low-power full-rate semi-digital delay-locked loop (DLL) architecture using an analog-based finite state machine (AFSM) and a polyphase filter. The AFSM architecture uses low-power analog blocks to map high-frequency loop feedback information to low frequency, thus reducing the total power required for digital signal processing and for the macro as a whole. The polypha...Show More
A Low-Jitter Sub-Sampling PLL With a Sub-Sampling DLL
A sub-sampling phase-locked loop (SSPLL) with a sub-sampling delay-locked loop is presented to extend the loop bandwidth and achieve the low jitter. A falling-edge tuning loop is added to align the falling edge of the reference clock with the rising one of the output clock. The proposed SSPLL is realized in a 0.18 {\mu }\text{m} CMOS process and its active area is 0.185mm2. At the output frequ...Show More
All-Digital Fast-Locking Delay-Locked Loop Using a Cyclic-Locking Loop for DRAM
Dong-Hoon Jung;Young-Jae An;Kyungho Ryu;Jung-Hyun Park;Seong-Ook Jung
A fast-locking all-digital delay-locked loop (DLL) with closed-loop duty-cycle correction (DCC) capability is proposed for clock synchronization in DRAM. A new cyclic-locking loop is proposed to resolve the locking speed degradation due to the replica delay line (RDL) in the DLL. The proposed cycliclocking loop operates asynchronously and offers an optimal loop delay for DLL lock...Show More
Fast-Lock Dual Charge Pump Analog DLL using Improved Phase Frequency Detector
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)
Year: 2007 | Conference Paper |
In this paper, a dual charge pump architecture for fast-lock low-jitter analog delay-locked loop (DLL) is proposed and analyzed. The proposed fast lock analog DLL takes up less area compared to other similar fast lock analog DLL due to the reduction of the number of phase frequency detector (PFD) used in the design. An improved PFD is proposed to reduce the output jitter by reduc...Show More
Design of low power DLL with TDC for jitter suppression
2015 Online International Conference on Green Engineering and Technologies (IC-GET)
Year: 2015 | Conference Paper |
This project proposes a 90° phase-shift delay-locked loop (DLL) used in dynamic RAM for data sampling clock generation and clock synchronization. In previous DLL, the mismatch between the delay line segments which caused the process variation in the circuit. This proposed DLL reduce the process variation issues and also minimize the area by adopting a multiplying DLL based ...Show More
A Novel High Speed 2-Step TDC-Based All-Digital DLL for DDR SDRAM Applications
2024 4th International Conference on Sustainable Expert Systems (ICSES)
Year: 2024 | Conference Paper |
In sequential digital systems both Delay Locked Loops (DLLs) and the Phase Locked Loops (PLLs) are utilized for enhanced timings, i.e., to reduce the detrimental effects of distortion and instability in the circuit. An effective DLL structure with a linear delay feature has been proposed in this work. Function is accomplished by altering traditional hardware architecture. A high-speed design...Show More
Jitter of Delay-Locked Loops Due to PFD
In this paper, delay-locked loop's (DLLs) jitter due to uncertainties in the phase frequency detector (PFD) is calculated. First, time-domain equations of the DLL are introduced. These equations are the key to obtaining a closed-form equation related to the jitter of DLL in presence of a noisy PFD. Jitter equations at the output of all stages are calculated theoretically. A DLL i...Show More
The Research of DLL Used in DS Spread Spectrum Communication System
2011 First International Conference on Instrumentation, Measurement, Computer, Communication and Control
Year: 2011 | Conference Paper |
In direct sequence (DS) spread spectrum communication system, the first condition of receiving correct data is chip synchronization. Delay-locked loop (DLL) is an important part of implementing chip synchronization in digital receiver. This paper explores fundamental of digital DLL, presents basic structure of it. Much attention has been paid for algorithm of phase detector and working...Show More
A Novel All Digital Delay Lock Loop (ADDLL)
2007 Internatonal Conference on Microelectronics
Year: 2007 | Conference Paper |
Cited by: Papers (1)
The use of delay locked loops (DLL) for clock recovery is currently receiving an increased interest. In this work a novel all digital DLL (ADDLL) circuit for data recovery is presented. The design is based on dividing the DLL circuit into independent groups of taps for optimum tap selection. A controller circuit is added to control tap switching. The ADDLL architecture is applied...Show More
The tracking accuracy of baseband DLL with AWN
2012 IEEE 11th International Conference on Signal Processing
Year: 2012 | Conference Paper |
The tracking accuracy of baseband Delay Locked Loop (DLL) with narrow loop band is studied. The equivalent phase discrimination model of code delay correlator is provided, and the correlation functions and power spectrum density functions of correlator output port noise and its equivalent noise at the input port are developed, then the simplified calculation equation of the tracking accuracy...Show More
Differential multi-phase DLL for reconfigurable radio frequency synthesizer
Javed S Gaggatur;Vishal Khatri;Immanuel Raja;Manas K Lenka;Gaurab Banerjee
2014 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)
Year: 2014 | Conference Paper |
Cited by: Papers (12)
A multiphase, delay-locked loop (DLL) based frequency synthesizer is designed for harmonic rejection mixing in reconfigurable radios. This frequency synthesizer uses a 1 GHz input reference frequency, and achieves ≤ 20ns settling time by utilizing a wide loop bandwidth. The circuit has been designed in 0.13-μm CMOS technology. It is designed for a frequency range of 500 MHz to 3 GHz with stu...Show More
Design and analysis of differential multiphase DLL for jitter and power optimization
2015 2nd International Conference on Recent Advances in Engineering & Computational Sciences (RAECS)
Year: 2015 | Conference Paper |
Cited by: Papers (2)
Phase detector (PD) and voltage controlled delay line(VCDL) is a main element in delay locked loop (DLL), the power optimized DLL is to generate multiple time/phase delay for different applications such as signal synchronization, VLSI applications and clock and data recovery. The performance of DLL depends upon Locked time, power consumption, time jitter and lock range. The main ...Show More
Multipath Effects on the Performance of DLL in a GNSS Receiver
Chinese Journal of Electronics
Cited by: Papers (2)
In order to improve the performance of a GNSS (Global navigation satellite system) receiver, multipath effects on common DLLs (Delay locked loops) are approached through comparisons with one coherent and three noncoherent DLLs under non-fading and fading conditions. The characteristics of multipath errors in DLL discriminators are analyzed and evaluated. Furthermore, the performance of DL...Show More
A digitally assisted 20MHz–600MHz 16-phase DLL enhanced with dynamic gain control loop
2015 European Conference on Circuit Theory and Design (ECCTD)
Year: 2015 | Conference Paper |
Cited by: Papers (2)
In the proposed low-jitter delay locked loop (DLL), the analog charge pump (CP) is replaced by combination of binary accumulator (ACC) and digital-to-analog converter (DAC) to solve the problem of achieving small loop gains and mirroring small currents. Also, the problem of leakage currents during the lock state is removed when DAC provides a fixed analog voltage based on the ACC's output di...Show More
A common source cascaded MOS feedback charge pump with wide lock in range for DLL
2016 International Conference on Signal Processing, Communication, Power and Embedded System (SCOPES)
Year: 2016 | Conference Paper |
Locking range of DLL (Delay Locked Loop) depends upon channel length modulation effect of CMOS. Via constant current source/sink Charge-pump adds/removes charges to/from a loop filter. A new feedback topology is used in proposed charge pump (CP) to reduce the current mismatch in charge pump mismatch for PET (Positron Emission Tomography) imaging applications. Simulations are performed in cad...Show More
This paper proposes a self-aligned sub-harmonically injection locked phase locked loop (SILPLL) in 180-nm Semi Conductor Laboratory (SCL) CMOS technology. In this work, an aperture phase detector (APD) based delay locked loop (DLL) with windowing technique is proposed to dynamically align the injection timing of pulse with the rising edge of sub-harmonically injection locked voltage controll...Show More
A 2.2-mW 20–135-MHz False-Lock-Free DLL for Display Interface in 0.15- \mu\hbox{m} CMOS
This brief describes a wide-range operating false-lock-free delay-locked loop (DLL) for a low-voltage differential signaling (LVDS) display interface. A false-lock detector circuit and a self-reset circuit internally prevent any possible false locks in a robust way. The proposed DLL immediately removes stuck false locks caused by an improper phase detector state. The DLL circuit ...Show More
A low power multi-band selector DLL with wide-locking range
2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial
Year: 2008 | Conference Paper |
A delay-locked loop of multi-band selector with wide- locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. T...Show More
A 2.7-Gb/s CDR Circuit Based on Multiplexed Recirculating Delay-Locked Loop for ±10%-SSC Clock-Embedded Display Interface
Ching-Yuan Yang;Yen-Kuei Lu;Miao-Shan Li;Tai-Yuan Chen;Chin-Lung Lin
A clock and data recovery (CDR) circuit based on a multiphase multiplexed recirculating delay-locked loop (MRDLL) is presented for spread-spectrum-modulation clock-embedded display interface. In the training stage, the MRDLL CDR is acting as a phase-locked loop (PLL) to generate sampling clocks. After the PLL is locked, the MRDLL CDR operates as a recirculating DLL to recover the incoming da...Show More
A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL
Ki-Won Lee;Joo-Hwan Cho;Byoung-Jin Choi;Geun-Il Lee;Ho-Don Jung;Woo-Young Lee;Ki-Chon Park;Yong-Suk Joo;Jae-Hoon Cha;Young-Jung Choi;Patrick B. Moran;Jin-Hong Ahn
Three circuit techniques for a 1.5 V, 512 Mb graphic DDR4 (GDDR4) SDRAM using a 90-nm DRAM process have been developed. First, a dual-clock system increases clocking accuracy and expands internal timing margins for harmonious core operation regardless of external clock frequency. Second, a four-phase data input strobe scheme helps to increase the input data valid window. Third, a fully analog dela...Show More
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