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Showing 1-25 of 18,465 resultsfor "Index Terms":Test Board
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The testability structure for digital circuits described in IEEE Std 1149.1 has been extended to provide similar facilities for mixed-signal circuits. The architecture is described, together with the means of control of and access to both analog and digital test data. Sample implementation and application details (which are not part of the standard) are included for illustration. Also, extensions ...Show More
This standard augments IEEE Std 1149.1 to improve the ability for testing differential and/or ac-coupled interconnections between integrated circuits on circuit boards and systems.Show More
Combining ATE and flying probe in-circuit test strategies for load board verification and test
Soh Ying Seah;Melanie Po-Leen Ooi;Ye Chow Kuang;Chee Sun See;Shanti Panchadcharam;Serge Demidenko
2009 IEEE Instrumentation and Measurement Technology Conference
Year: 2009 | Conference Paper |
Cited by: Papers (3)
Load board verification is normally performed by IC manufacturers on an automatic test equipment (ATE) as per of the standard test procedure prior to final test. Since test load boards are used as an interface between the automatic test equipment (ATE) and integrated circuit (IC), it is thus important to ensure that a particular load board is functioning otherwise the test integrity of all IC test...Show More
Circuitry that may be built into an integrated circuit to assist in the test, maintenance and support of assembled printed circuit boards and the test of internal circuits is defined. The circuitry includes a standard interface through which instructions and test data are communicated. A set of test features is defined, including a boundary-scan register, such that the component is able to respond...Show More
As printed circuit boards have decreased in size and increased in complexity (i.e. number of layers, number of installed components, speed of busses, etc.), access to test resources (i.e. probe points) necessary for sufficient printed circuit board test has diminished. The use of intrusive test methods such as in-circuit testers, manufacturing defect analyzers, and flying probe testers entails man...Show More
Study on Software of VXIbus Boundary Scan Test Generation
2007 8th International Conference on Electronic Measurement and Instruments
Year: 2007 | Conference Paper |
The goal of this paper is to develop a set of software of boundary-scan test (BST) generation using some test generation algorithms and test data. In order to get the test data quickly and effectively, a new innovative method of establishing test project description (TPD) file is presented. During the testing of two different boundary-scan circuit boards, all faults can be detected, indicating tha...Show More
Circuitry that may be built into an integrated circuit to assist in the test, maintenance and support of assembled printed circuit boards is defined. The circuitry includes a standard interface through which instructions and test data are communicated. A set of test features is defined, including a boundary-scan register, such that the component is able to respond to a minimum set of instructions ...Show More
Incorporating Design Research for Missile Testing in PXI Based on BIT and ATE
2007 8th International Conference on Electronic Measurement and Instruments
Year: 2007 | Conference Paper |
Cited by: Papers (1)
Progressively, built-in test (BIT) and automatic test equipment (ATE), synthesizing design and application, become the effective approach to improve complex system testability and maintainability. Widely, PXI (PCI extensions for Instrumentation) is applied to the domain of automated test. Analyzed on the configuration of resource, module design, system design, compatibility design, tolerated error...Show More
Chip Board Interaction Analysis of 22-NM Fully Depeleted Silicon on Insulator (FD-SOI) Technology in Wafer Level Packaging (WLP)
Jae Kyu Cho;Jens Paul;Simone Capecchi;Dirk Breuer;Frank Kuechenmeister;Doug Scott;JongJin Choi;Wonjoon Kang
2018 International Wafer Level Packaging Conference (IWLPC)
Year: 2018 | Conference Paper |
Cited by: Papers (1)
Recently, Wafer Level Packaging (WLP) has been in high demand, especially in mobile device applications as a path to enable miniaturization while maintaining good electrical performance. The relatively inexpensive package cost and simplified supply chain are encouraging other industries to adapt WLP capabilities for radio frequency (RF), communications/sensing (mmWave) and automotive applications....Show More
Export data related to motor vehicle pre-defined events in usage history is collected, recorded, stored, and exported by motor vehicle event data recorders (MVEDRs). A protocol for MVEDR output data compatibility and export protocols of MVEDR data elements is defined by this standard. A motor vehicle event data recorder connector lockout apparatus (MVEDRCLA) and a near field communication (NFC) pr...Show More
Methods for Automated PCB Testing - Requiarements, Rules and Implementation
2023 XXXII International Scientific Conference Electronics (ET)
Year: 2023 | Conference Paper |
For the verification of electronic devices, a test instruction is prepared with a specific strategy on what and how to test. The article discusses all the types of testing currently used to verify PCBs: bare board and assembled PCBs - where the functionality of the device is verified. An overview is given of the nature of each test, the sequence that is followed in the test, the equipment required...Show More
The aviation industry has many aircraft in use after more than twenty years of life with some aircraft achieving the fifty years of life milestone. The avionics aboard the older aircraft are based on circuitry elements with diminishing or no manufacturing sources. Entire families of integrated circuits are no longer available, such as the early Intel processors and peripherals, 54C series CMOS log...Show More
Obsolescence replacement and testing — reducing cost through commonality
Year: 2017 | Conference Paper |
IEEE Standard for Test Access Port and Boundary-Scan Architecture - Redline
IEEE Std 1149.1-2013 (Revision of IEEE Std 1149.1-2001) - Redline
Year: 2013 | Standard |
Cited by: Papers (21)
Circuitry that may be built into an integrated circuit to assist in the test, maintenance and support of assembled printed circuit boards and the test of internal circuits is defined. The circuitry includes a standard interface through which instructions and test data are communicated. A set of test features is defined, including a boundary-scan register, such that the component is able to respond...Show More
IEEE Standard for Automatic Test Markup Language (ATML) for Exchanging Automatic Test Equipment and Test Information via XML
This document specifies a framework for the automatic test markup language (ATML) family of standards. ATML allows automatic test system (ATS) and test information to be exchanged in a common format adhering to the extensible markup language (XML) standard.Show More
The Effectiveness of Board Committees and Governance Premium
2007 International Conference on Management Science and Engineering
Year: 2007 | Conference Paper |
This paper investigates whether the board committees can provide governance premiums, which means we examine whether the corporate with sub-committees could bring cumulative abnormal returns to the investors. Using the unbalanced panel data of 2235 company-years we find that the corporate with Nomination, Strategy and Audit committees can bring significant premiums to their investors, which means ...Show More
Reconfigurable PETPG for External Testing of Digital Circuits
Mahmoud Fathy Al-Sawah;Mohamed H. El-Mahlawy;Mohamed A. Abbass
2020 15th International Conference on Computer Engineering and Systems (ICCES)
Year: 2020 | Conference Paper |
Cited by: Papers (1)
In this paper, the application of the board-level external testing using the pseudo-exhaustive testing (PET) was explored. The new design approach to reconFigure the hardware of the pseudo-exhaustive test pattern generator (PETPG), based on the permutated convolved linear feedback shift register/shift register (LFSR/SR), is developed. The permutated convolved LFSR/SR is considered a superset of al...Show More
Lead-Free Solder Material and Chip Thickness Impact on Board-Level Reliability for Low-K WLCSP
This paper evaluates the effect of the solder ball material and chip thickness on board-level reliability using low-K wafer-level chip-scale packaging (WLCSP). The composition of the three evaluated solder ball materials includes SnAg1.0Cu0.5, SnAg2.0Cu0.5, and SnAg2.6Cu0.6. The chip thickness is ranging from 200, 300, and 775 ¿m. Initially, the high temperature storage and ten-time multiple reflo...Show More
The Overall Design of Multi-state Detection System of a Certain Wireless Communication Equipment Boards
2015 Sixth International Conference on Intelligent Systems Design and Engineering Applications (ISDEA)
Year: 2015 | Conference Paper |
Owing to the slow circuit board level maintenance and fault location of wireless communications equipment, and technically demanding problems, the multi-state circuit board testing environment was establish to study the circuit board interface type, input and output signals, power supply and others. Based on the diagnostic strategies of multi-signal flow model optimization design, this paper desig...Show More
Promoting and facilitating interoperability between components of automatic test systems where test results need to be shared is addressed in this standard. The standard thus facilitates the capture of test results data in storage devices and databases, facilitating online and offline analysis. The test results schema becomes a class of information that can be used within the SIMICA family of stan...Show More
Work in progress -test engineering program
Proceedings Frontiers in Education 35th Annual Conference
Year: 2005 | Conference Paper |
Cited by: Papers (1)
A pilot program of lectures and laboratory work in mixed-signal test development engineering has been initiated at San Jose State University with support from Agilent Technologies and National Semiconductor Corporation. Class one uses bench-top equipment and a specifically-designed printed circuit board to explore the basic issues of testing: accuracy, guard bands, design for test (DfT), DSP-based...Show More
Affordable Flying Probe-Inspired In-Circuit-Tester for Printed Circuit Boards Evaluation with Application in Test Engineering Education
Sorin Liviu Jurj;Raul Rotar;Flavius Opritoiu;Mircea Vladutiu
This paper presents a hybrid sensorless In-Circuit Tester (ICT) design by combining the features of Flying Probe Testing (FPT) and the capabilities of a Coordinate Measuring Machine (CMM). The experimental results show that the proposed Flying Probe-inspired ICT (FPICT) is suitable for smaller sized Printed Circuit Boards (PCBs) and proves efficient regarding precision (overall precision of 95.70%...Show More
Automation solution for Software Testing of CAN based ECUs
2021 Fourth International Conference on Electrical, Computer and Communication Technologies (ICECCT)
Year: 2021 | Conference Paper |
Cited by: Papers (2)
In contemporary vehicle electronics, ECUs are pre-eminent to effectuate the system and deliver the prolific features embedded within them. The paradigm shift to ECU technology has led to an increase in the complexity of the software that now has to render safety and diagnostic services along with functional solutions. Taking cognizance of this intricacy, the enhancement of testing methodologies to...Show More
PCB Testing Using Infrared Thermal Signatures
2005 IEEE Instrumentationand Measurement Technology Conference Proceedings
Year: 2005 | Conference Paper |
Cited by: Papers (6)
A printed circuit board (PCB) testing method using infrared thermal signatures is presented. The concept of thermal signature for PCBs is introduced. Based on this concept, the testing method is able to classify the integrated circuits (ICs) on a PCB into a number of classes (e.g. functional - fault free, non-functional - faulty and less reliable - functional circuits with high current consumption...Show More
IEEE Std 1581 defines a low-cost method for testing the interconnection of discrete, complex memory Integrated Circuits (ICs) where additional pins for testing are not available and implementing Boundary-Scan (IEEE 1149.1) is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behaviora...Show More
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