Showing 1-25 of 6,359 resultsfor "Index Terms":Part Of Package
"Index Terms":Part Of Package
- Sort
Get notified when new research is published matching your search criteria.
Sort By
Results
Advanced Enhanced High Heat Dissipation Package Structures
2007 IEEE Conference on Electron Devices and Solid-State Circuits
Year: 2007 | Conference Paper |
In high power density and deep sub-micron of package fabrications, it is difficult to maintain high heat dissipation on device; because of the higher pattern density and IO on IC design. A package with high heat dissipation, comprising a carrier and a chip located thereon, with electrical connection between the chip to the carrier. A molding compound is used to encapsulate the chip and the carrier...Show More
Guest Editors' Introduction: Big Innovations in Small Packages
IEEE Design & Test of Computers
Cited by: Papers (1)
Conventional single-die microelectronic packages on a printed circuit board have been with us for a long time. These electronic packages provide a means of interconnecting, powering, cooling, and protecting integrated circuit chips. Today, system-in-package (SiP) provides a variety of packaging requirements for computer, consumer, aerospace, military, and medical electronic applications by stackin...Show More
Waste reduction of returnable packaging: A case study of reverse logistics in an auto parts company
2015 IEEE International Conference on Industrial Engineering and Engineering Management (IEEM)
Year: 2015 | Conference Paper |
Cited by: Papers (1)
The objective of this research is to study and reduce waste of reverse logistics in an auto parts company. The result of this study shows that the main problem of packaging waste for packing auto parts used to transport among 3 countries is high. The studying start from collecting data that need for waste analyzing such as export costs of auto parts, packaging cost and export statistic of 2014. Th...Show More
Analysis and Experimental Study of the Package Stresses in a QFN Plastic-Encapsulated Package
Plastic-encapsulated packages are known to suffer package stress issues which often cause undesired shifts in the IC electrical parameters. Two types of package stress are analyzed and their contributions to the overall package stress in a Quad-Flat No-leads (QFN) Package are experimentally studied in this paper. The volumetric package stress generated by the mold compound is analyzed using the ma...Show More
Research on automatic sorting and distribution system of standard parts for air parts assembly
Guangku Xue;Xifeng Fan;Dapeng Liu;Yangbin Guo;Zhiqiang Li;Zhijun Peng;Qian Zhao
2020 IEEE 11th International Conference on Mechanical and Intelligent Manufacturing Technologies (ICMIMT)
Year: 2020 | Conference Paper |
Cited by: Papers (2)
The assembly of aviation parts is an extremely complicated project. A large part usually consists of thousands of small parts connected by various types of standard parts. Due to the low efficiency and informationization of the traditional manual logistics, it is unable to meet the requirements of the logistics technology of standard parts in the process of modern aviation parts assembly. Based on...Show More
Trends in semiconductor packaging, a merchant house view
Proceedings of the IEEE 1988 Custom Integrated Circuits Conference
Year: 1988 | Conference Paper |
Cited by: Papers (4)
Semiconductor packaging is being driven in two major directions by the demand for increased system operating speeds and higher functional density. Most prominent is the trend toward higher functional integration on the die, resulting in both a larger die size and decreased feature size. The other major trend is the mechanical integration of multiple devices in a single package. These trends requir...
Show More
First Page of the Article
Show MoreThe Development of Semiconductor Packaging and Testing Industry of China
2007 8th International Conference on Electronic Packaging Technology
Year: 2007 | Conference Paper |
The semiconductor industry of China develops rapidly. From 2001 to 2006, China IC industry keeps growing rapidly at an average yearly increase of 33.6%, much higher than the world IC industry increase. In 2006, China IC industry scales 100.63 billion RMB Yuan. China IC industry occupies a higher percentage from 1.9% of year 2001 to 6.1% of 2006. IC design, manufacturing, packaging and testing indu...Show More
Using contract manufacturing services to assist with design solutions in advanced packaging technologies
Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium
Year: 1997 | Conference Paper |
Electronic product companies (OEMs) face difficult problems today when dealing with the many divergent demand of bringing new products to market. These demands include: Higher system performance; greater feature set; reduced costs; reduced size and weight. Responding to these demands, engineers are increasingly turning to advanced packaging technologies for solutions. However, the best results fro...Show More
Development on Semiconductor Packaging and Testing Industry in China
2006 7th International Conference on Electronic Packaging Technology
Year: 2006 | Conference Paper |
China Electronics Packaging Society (CEPS) has organized several international conferences on electronics packaging technology and several small-scale proseminars to build a bridge for the people engaged in packaging industry home and abroad, so much so that it will play a helpful role in promoting China electronic packaging development and international cooperation & technical exchange.Show More
A Versatile Timing Microsystem Based on Wafer-Level Packaged XTAL/BAW Resonators With Sub-$\mu$ W RTC Mode and Programmable HF Clocks
David Ruffieux;Nicola Scolari;Frédéric Giroud;Thanh-Chau Le;Silvio Dalla Piazza;Felix Staub;Kai Zoschke;Charles-Alix Manier;Hermann Oppermann;Tommi Suni;James Dekker;Giorgio Allegato
This paper introduces and demonstrates with high yield a novel concept for the packaging under vacuum of tuning fork quartz XTALs on top of a silicon interposer equipped with TSVs. It paves the way to the implementation of a monolithic timing microsystem where the ASIC is part of the housing of a newly designed tiny 131-kHz XTAL to reach extreme module miniaturization (1.5$\,\times\,$1.1$\,\times\...Show More
A Versatile Timing Microsystem Based on Wafer-Level Packaged XTAL/BAW Resonators With Sub-$\mu$ W RTC Mode and Programmable HF Clocks
David Ruffieux;Nicola Scolari;Frédéric Giroud;Thanh-Chau Le;Silvio Dalla Piazza;Felix Staub;Kai Zoschke;Charles-Alix Manier;Hermann Oppermann;Tommi Suni;James Dekker;Giorgio Allegato
Semiconductor Packaging Materials Outlook
2006 11th International Symposium on Advanced Packaging Materials: Processes, Properties and Interface
Year: 2006 | Conference Paper |
Summary form only given. Semiconductor packaging materials are a key to the success of the semiconductor business in total. Changes in consumer electronics are driving the changes in packaging materials. This presentation highlights the market growth and trends in laminate substrates, lead frames, wafer level packaging dielectrics, bonding wire, encapsulants and molding compounds, thermal interfac...Show More
Overmold technology applied to cavity down ultrafine pitch PBGA package
The transfer molding technology is normally used for leadframe type packages and chip-up plastic ball grid array (PBGA) packages. This technology has been applied to cavity down PBGA packages where, normally, a liquid epoxy is dispensed by a needle in the cavity in order to cover the device and gold wires without exceeding the solder ball height plane. The new encapsulation approach using transfer...Show More
Advancing Chiplet Architecture Through Heterogeneous Integration on Laser-processed Glass Substrates
Richard Noack;Nils Anspach;Roman Ostholt;Daniel Dunker;Norbert Ambrosius
2024 IEEE 10th Electronics System-Integration Technology Conference (ESTC)
Year: 2024 | Conference Paper |
With the relentless drive for enhanced computing performance and system integration, the semiconductor industry is transitioning from traditional organic substrate packaging to innovative glass core integrations. This paper explores chiplet architecture heterogeneous integration within glass substrates, enabled by advancements in Laser Induced Deep Etching (LIDE) technology. Traditional organic su...Show More
Package Assembly Design Kits (PADK's)- The Future of Advanced Wafer-Level Manufacturing
2024 IEEE 10th Electronics System-Integration Technology Conference (ESTC)
Year: 2024 | Conference Paper |
Process design kits (PDKs) are well-known catalysts in integrated circuit (IC) design. However, they are still a new concept to the packaging world and many packaging engineers do not understand their importance in the success of IC designs. Traditionally, packaging companies provide only a copy of their design rules, which tend to be very dynamic. This approach creates unnecessary delays and back...Show More
Trends in Fan-out wafer and panel level packaging
Tanja Braun;Karl-Friedrich Becker;Markus Wöhrmann;Michael Töpper;Lars Böttcher;Rolf Aschenbrenner;Klaus-Dieter Lang
2017 International Conference on Electronics Packaging (ICEP)
Year: 2017 | Conference Paper |
Cited by: Papers (14)
The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies that also allow large area processing and 3D integration with strong potential for low cost applications. Here, Fan-Out Wafer Level Packaging [FOWLP] is one of the latest packaging trends in microelectronics. Besides developments to higher and heterogeneous integration ...Show More
High Density Multi-Chip Embedded Panel-Level Packaging Integration Technology
Xianming Chen;Benxia Huang;Yejie Hong;Lei Feng;Jindong Feng;Guilin Zhu;Gao Huang;Yanlin Dong;Wu Chen
2023 24th International Conference on Electronic Packaging Technology (ICEPT)
Year: 2023 | Conference Paper |
The development of advanced semiconductor packaging is focused on achieving high-density integration, superior performance, efficient thermal management, high reliability, ease of mass production, and low cost. This paper presents an innovative panel-level multi-chip embedded high-density packaging integration technology. It enables the establishment of electrical connections for single or doubles...Show More
Trends in microelectronics packaging and interconnection
Proceedings of 1995 Japan International Electronic Manufacturing Technology Symposium
Year: 1995 | Conference Paper |
Cited by: Papers (2)
Functions and definitions of electronics packaging - along with product-oriented electronics packaging and interconnection technologies, including roadmap and packaging requirements for portable electronics in the year 2000, are reviewed. It has been determined that high-density packaging is the major product driving force in today's highly competitive electronics industry. Accordingly, major tren...Show More
A low cost wafer level packaging process
Twenty Sixth IEEE/CPMT International Electronics Manufacturing Technology Symposium (Cat. No.00CH37146)
Year: 2000 | Conference Paper |
Cited by: Papers (2)
Semiconductors are currently connected to other system components by three main interconnect technologies: wirebond, TAB and solder bump. These processes are significant contributors to the cost of the bumped wafer. In the packaging industry, there is also a drive for towards wafer level packaging solutions in order to minimize the packaging cost and give high production rates. This paper describe...
Show More
First Page of the Article
Show MoreSystems engineering: a summary of electronics packaging techniques available for present and future systems
Third Annual IEEE Proceedings on ASIC Seminar and Exhibit
Year: 1990 | Conference Paper |
The different microelectronics packaging approaches currently available and in development are summarized for system engineers. Some of the important attributes the various approaches are pointed out. Some of the packaging issues a system engineer should consider when attempting to baseline a packaging approach are discussed. Four major categories of advanced packaging techniques are considered. T...Show More
Fast analysis and implementation of microelectronic packaging MSL with equal moisture distribution method
2016 17th International Conference on Electronic Packaging Technology (ICEPT)
Year: 2016 | Conference Paper |
With the rapid development of electronic packaging product design and manufacture, it is one of most concerned problems that how to provide reliable products to the market. One of the most time-consuming problems in the reliability analysis of microelectronic packaging is the problem of conventional heat and humidity sensitivity analysis. The non hermetic package in the microelectronic packaging i...Show More
A frugal integrated circuit packaging for non-planar surface-conformant electronics applications
Leonardo Shimizu Yojo;Favero Guilherme Santos;Louise Patron Etcheverry;Carlos R. P. Dos Santos Junior;Fagnaldo Braga Pontes;Elvio C. Dutra e Silva
2024 38th Symposium on Microelectronics Technology and Devices (SBMicro)
Year: 2024 | Conference Paper |
This work presents a proposal for semiconductor packaging for application in flexible electronics, with simplified manufacturing, aiming to create a low-cost alternative to meet the global demand for semiconductors. It consists of two layers: a base substrate and an interconnection substrate, which can be manufactured from FR-4 laminates, polyimide, polyamide, PET, PEN, and LCP. A proof of concept...Show More
Wafer-Level Flip Chip Packages Using Preapplied Anisotropic Conductive Films (ACFs)
Ho-Young Son;Chang-Kyu Chung;Myung-Jin Yim;Jin-Sang Hwang;Kyung-Wook Paik;Gi-Jo Jung;Jun-Kyu Lee
Recently, wafer-level packaging (WLP) has become one of the promising packaging technologies due to its advantages, such as fewer processing steps, lower cost, and enhanced device performance compared to conventional single-chip packaging. Many developments on new WLP design, material, and process have been accomplished according to performance and reliability requirement of the devices to be pack...Show More
How to Manipulate Warpage in Fan-out Wafer and Panel Level Packaging
Tanja Braun;Ole Hölck;Marius Adler;Mattis Obst;Steve Voges;Karl-Friedrich Becker;Rolf Aschenbrenner;Marcus Voitel;Marc Dreissigacker;Martin Schneider-Ramelow
2024 IEEE 74th Electronic Components and Technology Conference (ECTC)
Year: 2024 | Conference Paper |
Cited by: Papers (1)
Fan-out Wafer and Panel Level Packaging are two of the latest trends in microelectronics packaging. Both approaches come with different flavors as RDL last and RDL first and have reached maturity and are introduced in high volume manufacturing. Clear application trends and technology roadmaps do exist. This ranges from low density core technology for e.g. RF or PMIC (power management IC) packaging...Show More
IEEE Account
Purchase Details
Profile Information
Need Help?
- US & Canada: +1 800 678 4333
- Worldwide: +1 732 981 0060
- Contact & Support
- About IEEE Xplore
- Contact Us
- Help
- Accessibility
- Terms of Use
- Nondiscrimination Policy
- Sitemap
- Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest technical professional organization dedicated to advancing technology for the benefit of humanity.
© Copyright 2025 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.