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AdderNet 2.0: Optimal AdderNet Accelerator Designs With Activation-Oriented Quantization and Fused Bias Removal-Based Memory Optimization
IEEE Transactions on Circuits and Systems I: Regular Papers
Year: 2025 | Early Access Article |
Convolutional neural networks (CNNs) are computationally demanding due to expensive Multiply-ACcumulate (MAC) operations. Emerging neural network models, such as AdderNet, exploit efficient arithmetic alternatives like sum-of-absolute-difference (SAD) operations to replace the costly MAC operations, while still achieving competitive model accuracy as compared with the CNN counterparts. Nevertheles...Show More
SpikeNAS-Bench: Benchmarking NAS Algorithms for Spiking Neural Network Architecture
Genchen Sun;Zhengkun Liu;Lin Gan;Hang Su;Ting Li;Wenfeng Zhao;Biao Sun
IEEE Transactions on Artificial Intelligence
Year: 2025 | Early Access Article |
In recent years, Neural Architecture Search (NAS) has marked significant advancements, yet its efficacy is marred by the dependence on substantial computational resources. To mitigate this, the development of NAS benchmarks has emerged, offering datasets that enumerate all potential network architectures and their performances within a predefined search space. Nonetheless, these benchmarks predomi...Show More
BCIM: Constant-Time and High-Throughput Block-Cipher-In-Memory With Massively-Parallel Bit-Serial Execution
IEEE Transactions on Emerging Topics in Computing
Year: 2025 | Early Access Article |
In-memory computing (IMC) emerges as one of the most promising computing technologies for data-intensive applications to ameliorate the “memory wall” bottleneck in von Neumann computer systems. Meanwhile, IMC also shows promising prospects towards high- throughput and energy-efficient processing of cryptographic workloads. This paper presents Block-Cipher-In-Memory (BCIM), a constant-time, high- t...Show More
Compression of Respiratory Sound Signals via TranscoderQVAE
2024 IEEE Biomedical Circuits and Systems Conference (BioCAS)
Year: 2024 | Conference Paper |
Respiratory diseases are one of the most common causes of death worldwide. At present, digital stethoscopes are valuable tools for diagnosing respiratory diseases, but they face limitations in storage, computation, and transmission capabilities. Therefore, developing respiratory sound compression algorithms is crucial. In this work, we propose TranscoderQVAE (TQVAE). TQVAE adopts the idea of varia...Show More
Hardware Circuits and Systems Design for Post-Quantum Cryptography—A Tutorial Brief
Jiafeng Xie;Wenfeng Zhao;Hanho Lee;Debapriya Basu Roy;Xinmiao Zhang
Due to the increasing threats from possible large-scale quantum computers, post-quantum cryptography (PQC) has drawn significant attention from various communities recently. In particular, along with the National Institute of Standards and Technology (NIST) PQC standardization process, more works have gradually switched to the PQC hardware implementations. Following this trend, this tutorial brief...Show More
An MRI Compatible Data Acquisition Device for Rat Brain Recording Inside 16.4T Magnet
Concurrent recording of neural activities and functional magnetic resonance imaging (fMRI) data is useful for studying the neurovascular coupling relationship. This article presents a low-noise, frequency-shaping based neural recorder chip that is insensitive to radio frequency (RF) pulses and gradient echo artifacts under strong magnetic environment. To support simultaneous recording of local fie...Show More
WDVR-RAM: A 0.25–1.2 V, 2.6–76 POPS/W Charge-Domain In-Memory-Computing Binarized CNN Accelerator for Dynamic AIoT Workloads
Hongtu Zhang;Yuhao Shu;Qi Deng;Hao Sun;Wenfeng Zhao;Yajun Ha
In-memory computing (IMC) is an effective approach to accelerate the interference tasks of binary neural networks (BNN), which has been widely used in artificial intelligence of things (AIoT) applications. However, previous researches only focus on optimizing energy efficiency for a narrow voltage range. This poses a severe limitation for some AIoT applications, because they may have very dynamic ...Show More
A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-VDD Assist and Bitline Leakage Compensation
Yuqi Wang;Shen Zhang;Yifei Li;Jian Chen;Wenfeng Zhao;Yajun Ha
Compute SRAM (CSRAM) can be configured to execute efficient in-memory logic computation and search operations, which is made possible by the multirow activation scheme. Nevertheless, simultaneous multirow activation introduces notorious compute access disturbance in 6T-based CSRAM designs. Existing solutions aim to mitigate the disturbance issue via weakening the access transistor strength, clampi...Show More
WSQ-AdderNet: Efficient Weight Standardization based Quantized AdderNet FPGA Accelerator Design with High-Density INT8 DSP-LUT Co-Packing Optimization
Yunxiang Zhang;Biao Sun;Weixiong Jiang;Yajun Ha;Miao Hu;Wenfeng Zhao
2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD)
Year: 2022 | Conference Paper |
Cited by: Papers (5)
Convolutional neural networks (CNNs) have been widely adopted for various machine intelligence tasks. Nevertheless, CNNs are still known to be computational demanding due to the convolutional kernels involving expensive Multiply-ACcumulate (MAC) operations. Recent proposals on hardware-optimal neural network architectures suggest that AdderNet with a lightweight ℓ1-norm based feature extraction ke...Show More
Exploiting a Blink of Measurement Saturation Towards Hardware-Efficient Compressed Sensing Encoder Design
2022 IEEE International Symposium on Circuits and Systems (ISCAS)
Year: 2022 | Conference Paper |
This paper presents a hardware-efficient Saturation-Aware Compressed Sensing (SA-CS) encoder design exploiting the saturation arithmetic based accumulator architecture. The SA-CS encoder can label saturated measurements when a low-bitwidth accumulator is employed, thereby enabling the adoption of the saturation rejection CS recovery algorithm for successful signal reconstruction. Both the optimal ...Show More
CIMulator: A Computing in Memory Emulator Framework
In this brief, we present CIMulator, an open-source, extensible modeling, simulation, and emulation framework for on-chip digital Computing-In-Memory (CIM) design and assessment. Featuring a synthesizable Register Transfer Level (RTL) model, CIMulator encapsulates the fundamental in-memory bitline logic and the near-memory compute functionalities altogether. In this way, CIMulator ensures cycle-ac...Show More
A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations
Jian Chen;Wenfeng Zhao;Yuqi Wang;Yuhao Shu;Weixiong Jiang;Yajun Ha
To efficiently implement searching and logic functions with the SRAM-based in-memory computing (IMC), we need to perform computations on bitlines (BLs) (called compute access) via multiple wordline (WL) activations. However, this may cause prominent read disturbance when the IMC is implemented with the standard 6 T SRAM. To address this reliability issue, existing solutions adopt either auxiliary ...Show More
Artificial Intelligence Enables Real-Time and Intuitive Control of Prostheses via Nerve Interface
Diu Khue Luu;Anh Tuan Nguyen;Ming Jiang;Markus W. Drealan;Jian Xu;Tong Wu;Wing-kin Tam;Wenfeng Zhao;Brian Z. H. Lim;Cynthia K. Overstreet;Qi Zhao;Jonathan Cheng;Edward W. Keefer;Zhi Yang
Objective: The next generation prosthetic hand that moves and feels like a real hand requires a robust neural interconnection between the human minds and machines. Methods: Here we present a neuroprosthetic system to demonstrate that principle by employing an artificial intelligence (AI) agent to translate the amputee’s movement intent through a peripheral nerve interface. The AI agent is designed...Show More
Analysis and Design of Reconfigurable Sense Amplifier for Compute SRAM With High-Speed Compute and Normal Read Access
A compute SRAM requires high speed for both compute access and normal read access. However, it presents a very distinct bitline discharging behavior in these two modes, thus brings a significant challenge to the design of its sensing amplifiers. State-of-the-art sensing amplifiers, namely the symmetric single-ended sensing amplifier (SS-SA) and the asymmetric differential sensing amplifier (AD-SA)...Show More
A 55nm, 0.4V 5526-TOPS/W Compute-in-Memory Binarized CNN Accelerator for AIoT Applications
Hongtu Zhang;Yuhao Shu;Weixiong Jiang;Zihan Yin;Wenfeng Zhao;Yajun Ha
Binarized convolutional neural network (BCNN) is a promising and efficient technique toward the landscape of Artificial Intelligence of Things (AIoT) applications. In-Memory Computing (IMC) has widely been studied to accelerate the inference task of BCNN to maximize both throughput and energy efficiency. However, existing IMC circuits and architectures are only optimized for a fixed kernel size an...Show More
Analysis and Optimization Strategies Toward Reliable and High-Speed 6T Compute SRAM
In-SRAM Computation improves the throughput and energy-efficiency of data-intensive applications by utilizing parallelism and reducing the data transfers. However, when multiple wordlines are accessed simultaneously, a short-circuit path will likely incur dynamic read disturbance and generate extra direct current in 6T Compute SRAM (CSRAM). In order to mitigate this issue, existing works either de...Show More
A Wide Dynamic Range Neural Data Acquisition System With High-Precision Delta-Sigma ADC and On-Chip EC-PC Spike Processor
Jian Xu;Anh Tuan Nguyen;Tong Wu;Wenfeng Zhao;Diu Khue Luu;Zhi Yang
A high-performance, wide dynamic range, fully-integrated neural interface is one key component for many advanced bidirectional neuromodulation technologies. In this paper, to complement the previously proposed frequency-shaping amplifier (FSA) and high-precision electrical microstimulator, we will present a proof-of-concept design of a neural data acquisition (DAQ) system that includes a 15-bit, l...Show More
AxC-CS: Approximate Computing for Hardware Efficient Compressed Sensing Encoder Design
2019 32nd IEEE International System-on-Chip Conference (SOCC)
Year: 2019 | Conference Paper |
In this paper, we present an approximate computing framework for hardware-efficient compressed sensing encoder design exploiting application-level error-resiliency, termed as AxC-CS (Approximate Computing for Compressed Sensing). We consider a 2-stage scalar quantization scheme during CS encoding process for physiological signals in sensor nodes and demonstrate numerically that bringing forward th...Show More
Block-Sparse Modeling for Compressed Sensing of Neural Action Potentials and Local Field Potentials
2019 53rd Asilomar Conference on Signals, Systems, and Computers
Year: 2019 | Conference Paper |
Cited by: Papers (1)
This paper presents our attempt for the efficient sparse modeling and recovery for Compressed Sensing (CS) of extracellular neural action and local field potentials (APs & LFPs). Both type of neural signals can be modeled as block-sparse in DCT (Discrete-Cosine Transform) domain, where we exploit the spectral information to determine the block boundaries, including bandpass filter pole information...Show More
Area-Efficient Distributed Arithmetic Optimization via Heuristic Decomposition and In-Memroy Computing
2019 IEEE 13th International Conference on ASIC (ASICON)
Year: 2019 | Conference Paper |
Cited by: Papers (3)
Distributed arithmetic (DA) is popularly adopted in many digital signal processing (DSP) applications, such as filtering, linear transformations and convolutions, with both area and energy benefits. DA utilizes Look-Up Tables (LUTs) that are implemented with SRAM to store all possible precomputed results. However, a direct implementation will lead to exponential LUT size increase with respect to t...Show More
A Lightweight Deep Compressive Model for Large-Scale Spike Compression
2018 IEEE Biomedical Circuits and Systems Conference (BioCAS)
Year: 2018 | Conference Paper |
Cited by: Papers (5)
In this paper, we developed a deep learning-based compression model to reduce the data rate of multichannel action potentials in neural recording experiments. The proposed compression model is built upon a deep compressive autoencoder (CAE) with discrete latent embeddings. The encoder network of CAE is equipped with residual transformations to extract representative features from spikes, which are...Show More
A Low-Noise, Wireless, Frequency-Shaping Neural Recorder
Jian Xu;Anh Tuan Nguyen;Wenfeng Zhao;Hongsun Guo;Tong Wu;Harvey Wiggins;Edward W. Keefer;Hubert Lim;Zhi Yang
This paper presents a low-noise, wireless neural recorder that has a frequency dependent amplification to remove electrode offset and to attenuate motion artifacts. The recorder has 2.5 GQ and 50 MQ input impedance at 20 Hz and 1 kHz for recording local field potentials and extracellular spikes, respectively. To reduce the input-referred noise, we propose a low-noise frontend design with multiple ...Show More
On-Chip Neural Data Compression Based On Compressed Sensing With Sparse Sensing Matrices
On-chip neural data compression is an enabling technique for wireless neural interfaces that suffer from insufficient bandwidth and power budgets to transmit the raw data. The data compression algorithm and its implementation should be power and area efficient and functionally reliable over different datasets. Compressed sensing is an emerging technique that has been applied to compress various ne...Show More
BVF: Enabling Significant On-Chip Power Savings via Bit-Value-Favor for Throughput Processors
2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
Year: 2017 | Conference Paper |
Power reduction is one of the primary tasks for designing modern processors, especially for high-performance throughput processors such as GPU due to their high power budget. In this paper, we propose a novel circuit-architecture co-design scheme to harvest enormous power savings for GPU on-chip SRAM and interconnects. We propose a new 8T SRAM that exhibits asymmetric energy consumption for bit va...Show More
Analysis and design of energy-efficient data-dependent SRAM
2017 IEEE 12th International Conference on ASIC (ASICON)
Year: 2017 | Conference Paper |
Improving the energy efficiency of on-chip SRAM is a crucial task in memory-intensive system designs. This paper presents design considerations and architectural exploration for energy-efficient data-dependent SRAMs, in which the power consumption depends on the data stored in the bitcells. We further categorize the data-dependent SRAM designs into two broad types, i.e., distance-based SRAM and we...Show More
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