Showing 1-25 of 5,098 resultsfor "Index Terms":Interconnecting Layer
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Ru ALD With Bulk-Like Resistivity for Interconnects
Michael Breeden;Victor Wang;Ravindra Kanjolia;Mansour Moinpour;Jacob Woodruff;Harsono Simka;Andrew Kummel
2022 IEEE International Interconnect Technology Conference (IITC)
Year: 2022 | Conference Paper |
Cited by: Papers (2)
Ruthenium is viewed as a promising alternative to Cu and Co interconnect metals at M0/M1 interconnect layers due to its lower effective resistivity in highly-confined layers and vias, as well as its resistance to diffusion into porous low-k dielectrics and to electromigration. Atomic layer deposition of Ru has been reported with a variety of precursors, but the search for a Ru ALD process with a c...Show More
A Cross-Layer Architecture of Wireless Sensor Networks for Target Tracking
We propose the Low Energy Self-Organizing Protocol (LESOP) for target tracking in dense wireless sensor networks. A cross-layer design perspective is adopted in LESOP for high protocol efficiency, where direct interactions between the Application layer and the Medium Access Control (MAC) layer are exploited. Unlike the classical Open Systems Interconnect (OSI) paradigm of communication networks, t...Show More
Atomic layer deposition enabled interconnect technology for vertical nanowire array devices
Myongjai Lee;Jen-Hau Cheng;Kris Bertness;Norman Sanford;Dragos Seghete;Steven George;Y.C. Lee
TRANSDUCERS 2009 - 2009 International Solid-State Sensors, Actuators and Microsystems Conference
Year: 2009 | Conference Paper |
In this study, we have demonstrated atomic layer deposition (ALD) enabled interconnection technology for vertical, as-grown c-axis oriented GaN nanowire (NW) arrays encapsulated by benzocyclobutene (BCB). The nano-scaled ALD multilayer is essential to provide conformal dielectric/conductor coverage and precise thickness control for NW interconnects. Cross-sectional images taken in a focused ion be...Show More
Design and Fabrication of Stretchable Multilayer Self-Aligned Interconnects for Flexible Electronics and Large-Area Sensor Arrays Using Excimer Laser Photoablation
Stretchable interconnects are fabricated on polymer substrates using metal patterns both as functional interconnect layers and as in situ masks for excimer laser photoablation. Single-layer and multilayer interconnects of various designs (rectilinear and “meandering”) have been fabricated, and certain “meandering” interconnect designs can be stretched up to 50% uniaxially while maintaining good el...Show More
Optimization of Interconnecting Layers for Double- and Triple-Junction Polymer Solar Cells
Abu Farzan Mitul;Lal Mohammad;Bjorn Vaagensmith;Ashish Dubey;Devendra Khatiwada;Qiquan Qiao
IEEE Journal of Photovoltaics
Cited by: Papers (8)
In solution-processed tandem polymer solar cells, one of the most challenging parts is the optimization of interconnecting layers (ICLs) between subcells. In this study, ICLs were optimized for double- and triple-junction polymer solar cells. We investigated the robustness of PEDOT:PSS/AZO/PEIE ICL for tandem polymer solar cells. Solvent testing for ICL robustness showed a uniform coverage of the ...Show More
Thermal ALD of Cu via reduction of CuxO films for the advanced metallization in spintronic and ULSI interconnect systems
Steve Mueller;Thomas Waechtler;Lutz Hofmann;André Tuchscherer;Robert Mothes;Ovidiu Gordan;Daniel Lehmann;Francisc Haidu;Marcel Ogiewa;Lukas Gerlich;Shao-Feng Ding;Stefan E. Schulz;Thomas Gessner;Heinrich Lang;Dietrich R.T. Zahn;Xin-Ping Qu
In this work, an approach for copper atomic layer deposition (ALD) via reduction of CuxO films was investigated regarding applications in ULSI interconnects, like Cu seed layers directly grown on diffusion barriers (e. g. TaN) or possible liner materials (e. g. Ru or Ni) as well as non-ferromagnetic spacer layers between ferromagnetic films in GMR sensor elements, like Ni or Co. The thermal CuxO A...Show More
Thermal ALD of Cu via reduction of CuxO films for the advanced metallization in spintronic and ULSI interconnect systems
Steve Mueller;Thomas Waechtler;Lutz Hofmann;André Tuchscherer;Robert Mothes;Ovidiu Gordan;Daniel Lehmann;Francisc Haidu;Marcel Ogiewa;Lukas Gerlich;Shao-Feng Ding;Stefan E. Schulz;Thomas Gessner;Heinrich Lang;Dietrich R.T. Zahn;Xin-Ping Qu
Year: 2011 | Conference Paper |
Decentralized adaptive iterative learning control for nonaffine nonlinear interconnected systems
2009 7th Asian Control Conference
Year: 2009 | Conference Paper |
In this paper, we present an iterative learning controller for interconnected nonlinear nonaffine systems with repeatable control tasks. A local learning controller for each subsystem is constructed by a fuzzy neural learning component and a robust learning component to adaptively compensate for the nonaffine nonlinearities and interconnections. The fuzzy neural learning component is designed base...Show More
Peculiarities of surface plasmon excitation in amplifying Kretschmann structure: Correct wavelength-scale analysis by the method of single expression
Hovik V. Baghdasaryan;Tamara M. Knyazyan;Tamara T. Hovhannisyan;Marian Marciniak
2011 13th International Conference on Transparent Optical Networks
Year: 2011 | Conference Paper |
Cited by: Papers (3)
Traditional Kretschmann structure with dielectric covering layer of different thickness is analysed numerically by the method of single expression. Covering layers of some hundred nanometers exhibit waveguiding features and their excitation is possible at angles less than angle of surface plasmon excitation. Inclusion of gain in a covering layer is analysed and compensation of intrinsic loss in a ...Show More
Reverse Templating Effects of Low-Resistivity Ru ALD on Sputtered Ru
Victor Wang;Chenghsuan Kuo;Ravindra Kanjolia;Mansour Moinpour;Jacob Woodruff;Harsono Simka;Andrew C. Kummel
Ruthenium is a promising candidate to replace Cu as an interconnect metal due to its low resistivity in narrow vias and resistance to electromigration. In previous work, a Ru Atomic Layer Deposition (ALD) process using Ru(CpEt)2 and O2 was developed to produce films with bulk-like resistivities. However, the ALD exhibits poor initial nucleation with variable initial nucleation delay causing thickn...Show More
Enhancing the electromigration resistance of copper interconnects
G. Dixit;D. Padhi;S. Gandikota;J. Yahalom;S. Parikh;N. Yoshida;K. Shankaranarayanan;J. Chen;N. Maity;J. Yu
Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)
Year: 2003 | Conference Paper |
Cited by: Papers (3)
Various factors such as grain boundary/surface diffusion as well as structural properties of materials are known to affect the final electro-migration (EM) behavior of copper interconnections. Results presented in this paper show that the barrier layer has a strong influence in controlling the width of EM failure distributions. EM tests of samples with alternate barrier, fill and capping layers sh...Show More
High performance InP HEMT technology with multiple interconnect layers for advanced RF and mixed signal circuits
W. Ha;K. Shinohara;Z. Griffith;M. Urteaga;P. Chen;P. Rowell;B. Brar
2009 IEEE International Conference on Indium Phosphide & Related Materials
Year: 2009 | Conference Paper |
Cited by: Papers (6)
We report the development of high performance InP high electron mobility transistors (HEMTs) supported with three interconnect metal layers suitable for advanced RF and mixed signal integrated circuits. Depletion and enhancement mode devices with 35 nm gate-lengths are available with fT / fmax of 536/307 GHz and fT/fmax of 550/346 GHz, respectively. The process shows excellent device uniformity, y...Show More
Modelling and Analysis of Lower Metal On-Chip Interconnects Using Physical Fabrication Parameters
2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)
Year: 2019 | Conference Paper |
This paper looks into the modelling and analysis of on-chip interconnects in the lower metal region of an Integrated Circuit (IC). A proposed π-interconnect model is quantitatively modelled and analysed and the delay time, td is used as a metric to measure performance change from ideal circuit simulations for varying interconnect lengths using a driver-load inverter pair. The π-model delay time pe...Show More
Optimization of quality of service requirements for real-time applications using Cross Layer Design
AFRICON 2009
Year: 2009 | Conference Paper |
The evolution of the Next Generation heterogeneous Networks relies on the improved services that these networks can provide to real-time applications. Applications running on wired networks work seamlessly with the Open Systems Interconnect (OSI) protocol stack implementation. Its modularity eases functionality and improves performance of these applications. However, the channel conditions for wir...Show More
Strapped Cu interconnect for enhancing electromigration limit for power device application
2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD)
Year: 2020 | Conference Paper |
Cited by: Papers (1)
Current can cause electromigration (EM) damage in power device interconnects, thus the current density should be properly controlled. Lowering the current density requires placing and routing wide interconnects, increasing the die size. Therefore, enhanced EM entitlement would help to reduce the die size. Towards this goal, we have investigated the impact of strapped Cu interconnects on EM perform...Show More
Performance Improvement in SC-MLGNRs Interconnects Using Interlayer Dielectric Insertion
Due to their higher resistance, single layer graphene nanoribbons (GNRs) are not suitable for high-speed on-chip interconnect applications. Hence, we use multilayer GNRs (MLGNRs) that offer multiple conduction channels and lower resistance. However, MLGNRs turn into graphite as the number of layers increase, which reduces the mean-free path of each layer. Insertion of a dielectric between GNR laye...Show More
High performance InP mHEMTs on GaAs substrate with multiple interconnect layers
Wonill Ha;Zach Griffith;Dae-Hyun Kim;Peter Chen;Miguel Urteaga;Bobby Brar
2010 22nd International Conference on Indium Phosphide and Related Materials (IPRM)
Year: 2010 | Conference Paper |
Cited by: Papers (3)
We report the development of high performance metamorphic InP high electron mobility transistors (mHEMTs) with InAs composite channel design and three interconnect metal layers suitable for advanced RF and mixed signal integrated circuits. An un-passivated 35 nm Lg device showed RF figures-of-merit of 533 GHz fτ and 343 GHz fmax. After full circuit processing, encapsulated in BCB, a 35 nm Lg, 2 × ...Show More
Delay-Driven and Antenna-Aware Layer Assignment in Global Routing Under Multitier Interconnect Structure
A multilayer routing system usually adopts multiple interconnect configuration with different wire sizes and thicknesses. Since thicker layers of metal lead to fatter wires with smaller resistance, the layer assignment (LA) of nets has a large impact on the interconnect delay. However, such layer-dependent characteristics have been ignored by most of the state-of-the-art academic LA methods. These...Show More
Surface plasmon interaction with amplifying MQWs in multilayer kretschmann structure: Wavelength-scale analysis by the method of single expression
Hovik V. Baghdasaryan;Tamara M. Knyazyan;Tamara T. Hovhannisyan;Marian Marciniak
2012 14th International Conference on Transparent Optical Networks (ICTON)
Year: 2012 | Conference Paper |
Cited by: Papers (2)
Surface plasmons are promising candidates in realization of short distance optical interconnection. However an unavoidable material loss even in noble metals prevents their wide application. Covering dielectric layer of some hundred-nanometer thickness deposited upon the thin metal layer in Kretschmann configuration can operate as a plasmon supported waveguide with lower loss than the bare plasmon...Show More
A 206–294GHz 3-stage amplifier in 35nm InP mHEMT, using a thin-film microstrip environment
2010 IEEE MTT-S International Microwave Symposium
Year: 2010 | Conference Paper |
Cited by: Papers (3)
We present a compact, 3-stage millimeter-wave monolithic integrated circuit (MMIC) amplifier with an operating frequency of 206-294 GHz, formed by common-source configured 35 nm Lg InP mHEMTs and a multi-layer thin-film microstrip (TFM) wiring environment. The amplifier S21 mid-band gain is 11-16 dB, 3 dB bandwidth at 294 GHz, and 82.5 mW PDC. This is the first reported InP HEMT MMIC operating in ...Show More
A technique for fast calculation of capacitance matrices of interconnect structures
A finite difference (FD) method for rapid and accurate evaluation of capacitance matrices of interconnect configurations is described in this paper. The method utilizes newly-developed perfectly matching layer (PML) technique for mesh truncation, specially adapted to the static case in conjunction with a mixed boundary condition, referred to as the /spl alpha/-technique. The application of propose...Show More
Modeling RF Signal Propagation Along On-Chip Interconnects and the Effect of Substrate Doping with the Alternating-Direction-Implicit Finite-Difference Time-Domain (ADI-FDTD) Method
Conference Record of the 2006 Twenty-Seventh International Power Modulator Symposium
Year: 2006 | Conference Paper |
Cited by: Papers (2)
The alternating-direction-implicit finite-difference time-domain (ADI-FDTD) method is used to analyze metal-insulator-semiconductor-metal interconnects by solving Maxwell's equations in the time domain. This analysis shows that the silicon substrate losses and the metal line losses can be modeled with high resolution. Our modeling method is supported by experimental data. We find that semiconducto...Show More
Heat Transport in Graphene Interconnect Networks With Graphene Lateral Heat Spreaders
We simulated heat propagation in the integrated graphene heat spreaders within the interconnect hierarchy. In the considered design, the graphene layers perform the dual functions of interconnects and heat spreaders. We investigated Joule heating effects within the chip with graphene interconnect networks and heat spreaders. Numerical solutions for direct current and heat propagation equations wer...Show More
Validation of submodel technique for fracture evaluation in wafer-level package under thermal loading
2019 20th International Conference on Electronic Packaging Technology(ICEPT)
Year: 2019 | Conference Paper |
Cited by: Papers (1)
Through Silicon Via (TSV) is a key technique in wafer manufacturing and 3D integration for wafer level package. However, due to the large mismatch in thermal expansion coefficient under thermal loading, stress induced by TSV-Cu may drive deformation and cracks of the back-end-of-line (BEOL) layers. Because of the significant difference of length dimension for TSV devices, submodel technique is use...Show More
Cosputtered Cu/Ti Bonded Interconnects With a Self-Formed Adhesion Layer for Three-Dimensional Integration Applications
IEEE Electron Device Letters
Cited by: Papers (21)
A novel 3-D bonding technology with cosputtered copper and titanium as bonding material is proposed and investigated based on the diffusion mechanism of cosputtered metal during bonding. This technology features a self-formed adhesion layer for Cu metal layers and interconnects. In addition, cosputtered Cu/Ti bonding exhibits good electrical performance as well as high resistance to multiple curre...Show More
Low-loss through silicon Vias (TSVs) for RF system 3D integration
2022 IEEE 10th Asia-Pacific Conference on Antennas and Propagation (APCAP)
Year: 2022 | Conference Paper |
The TSV adapter board in a micro-system based on TSV technology is studied and a transmission structure was proposed which was stacked by three layers of silicon-based packaging. The electromagnetic model of the transmission structure is established and the simulation analysis is carried out. The result shows that the insertion loss (IL) of the transmission structure is below -0.37 dB and the retu...Show More
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