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Performance of Plasmonic Side-Coupled Waveguide Photodetector with Varying Schottky Barrier Height
2021 International Conference on Numerical Simulation of Optoelectronic Devices (NUSOD)
Year: 2021 | Conference Paper |
The impact of Schottky barrier height (SBH) on the performance of a side-coupled plasmonic waveguide photodetector (WGPD) is theoretically investigated by 3D opto-electrical simulations. A general decrease of the cut-off frequency is observed for all studied barrier heights (0.1 eV to 0.6 eV), most pronounced in the range (0.3 - 0.4) eV. The degradation is an electrostatic effect caused by the for...Show More
Scaled III-V optoelectronic devices on silicon
P. Tiwari;S. Mauthe;N. Vico Trivino;P. Staudinger;M. Scherrer;P. Wen;D. Caimi;M. Sousa;H. Schmid;K. E. Moselund;Q. Ding;A. Schenk
2020 International Conference on Numerical Simulation of Optoelectronic Devices (NUSOD)
Year: 2020 | Conference Paper |
Cited by: Papers (1)
In the present talk we discuss the development of the epitaxial technique Template-Assisted Selective Epitaxy (TASE)and its application for the monolithic integration of scaled III - V active photonic devices on silicon. A unique advantage of TASE for silicon photonics applications is that it enables a truly local integration of III-V material at precisely defined positions, it is therefore partic...Show More
Scaling Effects on the Plasmonic Enhancement of Butt-Coupled Waveguide Photodetectors
2020 International Conference on Numerical Simulation of Optoelectronic Devices (NUSOD)
Year: 2020 | Conference Paper |
We employed 3D opto-electrical simulations to study the scaling effects of a plasmonic structure on the optical performance of butt-coupled waveguide photodetectors by placing an Ag stripe on top of the intrinsic region. It is found that cutoffs which are limited by carrier drift in the high-field region of the non-plasmonic device improve with longer and wider stripe, while the metal thickness ha...Show More
Impact of Interface Traps and Zn Diffusion on Performance of Lateral Hybrid III-V/Si Photodetectors
2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
Year: 2020 | Conference Paper |
This paper attempts to gain insight into the physical mechanisms related to device performance of a recently reported hybrid III-V/Si waveguide-coupled photodetector with lateral current collection (LCC-PD) using coupled 3D optical and 2D electrical simulations. We demonstrate that Zn diffusion, a widely observed phenomenon for p-doped III-V materials, could increase the dark current and lower the...Show More
Ultra-Thin III-V Photodetectors Epitaxially Integrated on Si with Bandwidth Exceeding 25 GHz
Svenja Mauthe;Yannick Baumgartner;Saurabh Sant;Qian Ding;Marilyne Sousa;Lukas Czornomaz;Andreas Schenk;Kirsten E. Moselund
2020 Optical Fiber Communications Conference and Exhibition (OFC)
Year: 2020 | Conference Paper |
Effect of Stacking Faults on the Thermoelectric Figure of Merit of Si Nanowires
2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
Year: 2019 | Conference Paper |
The efficiency of converting waste heat to electricity requires a large value of the thermoelectric Figure of merit (ZT). This can be achieved by patterning bulk material into nanostructures like nanowires (NWs). Further improvement results from an increased surface roughness (SR) of such NWs [1]. In this work, Si NWs with stacking faults (SFs) are studied. It is shown that SFs can significantly r...Show More
Variability in the Characteristics of InGaAsSb/InAs Tunnel FETs Caused by Dopant-induced Traps
2019 Electron Devices Technology and Manufacturing Conference (EDTM)
Year: 2019 | Conference Paper |
Cited by: Papers (1)
In this paper, an attempt is made to understand the dopant-induced traps near the hetero-interface as a source of variability in InGaAsSb/InAs Tunnel FETs (TFETs). Comparing simulated and measured variability data suggests that a characteristic energy η=50 meV of the induced density-of-states (DOS) tail yields the best match with the experimental distribution of the sub-threshold swing (SS). Densi...Show More
Trap-Aware Compact Modeling and Power-Performance Assessment of III-V Tunnel FET
Yang Xiang;Dmitry Yakimets;Saurabh Sant;Elvedin Memisevic;Marie Garcia Bardon;Anne S. Verhulst;Bertrand Parvais;Andreas Schenk;Lars-Erik Wernersson;Guido Groeseneken
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
Year: 2018 | Conference Paper |
We report, for the first time, on a SPICE simulation study of the circuit-level power-performance impact of device traps in a state-of-the-art III-V heterojunction tunnel FET (TFET). First, the individual parasitic effects of junction bulk traps and oxide interface traps are incorporated in a compact model and validated against measurement-calibrated TCAD data, where we propose an analytical formu...Show More
InGaAs-on-Insulator FinFETs with Reduced Off-Current and Record Performance
C. Convertino;C. Zota;S. Sant;F. Eltes;M. Sousa;D. Caimi;A. Schenk;L. Czornomaz
2018 IEEE International Electron Devices Meeting (IEDM)
Year: 2018 | Conference Paper |
Cited by: Papers (26)
In this work, we demonstrate InGaAs-on-lnsulator FinFETs on silicon with optimized on/off trade-off showing record performance. This is achieved by using carefully designed source/drain spacers and doped extensions to mitigate the off-current, typically high in narrow band-gap materials, as part of a CMOS compatible replacement-metal-gate process flow. Using this technology, devices with LG = 20 n...Show More
Modeling whispering gallery mode III–V micro-lasers monolithically integrated on silicon
S. Sant;A. Schenk;B. Mayer;S. Wirths;S. Mauthe;H. Schmid;K. E. Moselund
2018 International Conference on Numerical Simulation of Optoelectronic Devices (NUSOD)
Year: 2018 | Conference Paper |
Cited by: Papers (2)
The vision to speed up on-chip data communication by signal multiplexing using light and the promise to reduce the energy consumption of interconnects using optoelectronic devices has boosted on-chip photonics during the past years. Silicon is an ideal material for optical waveguides and passives, but due to the indirect band gap it is an inefficient emitter. Promising techniques to integrate III-...Show More
Effect of Electron-phonon Scattering on the Thermal Conductivity of Si Nanowires
2018 48th European Solid-State Device Research Conference (ESSDERC)
Year: 2018 | Conference Paper |
Even though the effect of electron-phonon scattering on the electronic properties of Si nanowires has been widely studied, its impact on phonon transport has received much less attention. Recent experiments gave the first evidence of a doping-induced reduction of the thermal conductivity in highly B-doped \pmb( ~ 5×1019 cm-3) Si nanowires with a diameter of 31 nm. Here, we present a model that can...Show More
Ballistic Mobility Model for QDD Simulation of Ultra-short Transistors
2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM)
Year: 2018 | Conference Paper |
Cited by: Papers (1)
A local TCAD model of the ballistic mobility is proposed that can be used in quantum drift-diffusion (QDD) simulations. It can be combined with models for density gradient correction and source-to-drain tunneling (STDT). These quantum effects strongly affect the transfer characteristics of In0.53Ga0.47As double-gate ultra-thin-body (DG UTB) FETs with ultra-short channels.Show More
2D and 3D TCAD simulation of III-V channel FETs at the end of scaling
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
Year: 2018 | Conference Paper |
Cited by: Papers (1)
Quantum drift diffusion corrections and a simple ballistic mobility model are used to simulate IdVgs-characteristics of scaled 2D and 3D III-V channel FETs. The sub-threshold swing of double-gate ultra-thin-body geometries is extracted for different gate lengths, and the semi-classical results are compared with those from the quantum transport simulator QTx. The ballistic mobility recovers the QTx...Show More
Impact of Floating Body Effect, Back-Gate Traps, and Trap-Assisted Tunneling on Scaled In0.53Ga0.47As Ultrathin-Body MOSFETs and Mitigation Measures
Saurabh Sant;Paulina Aguirre;Herwig Hahn;Veeresh Deshpande;Lukas Czornomaz;Andreas Schenk
Ultrathin-body (UTB) III-V channel MOSFETs are known to suffer from the floating body effect which turns on a parasitic bipolar junction transistor (BJT) and increases the off-state leakage current. This paper presents a TCAD simulation study of UTB In0.53Ga0.47As n-channel MOSFETs with nanowire and planar device geometry, each with different gate lengths (LG) ranging from 13 to 300 nm. A single s...Show More
A scaled replacement metal gate InGaAs-on-Insulator n-FinFET on Si with record performance
H. Hahn;V. Deshpande;E. Caruso;S. Sant;E. O'Connor;Y. Baumgartner;M. Sousa;D. Caimi;A. Olziersky;P. Palestri;L. Selmi;A. Schenk;L. Czornomaz
2017 IEEE International Electron Devices Meeting (IEDM)
Year: 2017 | Conference Paper |
Cited by: Papers (16)
We demonstrate a scaled replacement-metal-gate InGaAs-on-Insulator n-FinFET on Si with LG = 13 nm and record Ion of 249 μA/μm at fixed Ioff = 100 nA/μm and Vd = 0.5 V. A subthreshold swing in saturation of 89 mV/dec and a Ron of 355 Ω-μm is also achieved. We further investigate the transport mechanisms at play in order to shed light on the contribution from short-channel effects and carrier genera...Show More
The impact of hetero-junction and oxide-interface traps on the performance of InAs/Si and InAs/GaAsSb nanowire tunnel FETs
A. Schenk;S. Sant;K. Moselund;H. Riel;E. Memisevic;L.-E. Wernersson
2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
Year: 2017 | Conference Paper |
Cited by: Papers (4)
Fabricated InAs/Si and InAs/GaAsSb vertical nanowire tunnel FETs are analyzed by physics-based TCAD with emphasis on the impact of hetero-junction and oxide-interface traps on their performance. After careful fitting of a minimum set of parameters, the effects of diameter scaling and gate alignment are predicted. Trap-assisted tunneling at the oxide interface is suppressed by scaling the diameter ...Show More
DFT-based analysis of the origin of traps at the InAs/Si (111) interface
2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
Year: 2017 | Conference Paper |
Trap-assisted tunneling is known to detrimentally affect the performance of TFETs. To find the origin of traps at the InAs/Si interface, Density Functional Theory (DFT) based modeling of the interface is performed using the DFT tool CP2K. Geometrically optimized atomic positions at the InAs/Si interface obtained by using structural minimization are in qualitative agreement with TEM images reported...Show More
Modeling the effect of surface roughness on the performance of line tunnel FETs
2017 47th European Solid-State Device Research Conference (ESSDERC)
Year: 2017 | Conference Paper |
Surface roughness causes random shifts in the lowest sub-band level around its ideal position. This gives rise to tail states of an otherwise step-like DOS of the 2D electron gas in the channel. These tail states cause a gradual onset of tunneling in a TFET with vertical tunnel paths and degrade the sub-threshold swing. The impact of roughness of the semiconductor/oxide interface on the transfer c...Show More
The influence of channel quantization and interface traps on the performance of InAs/Si pTFETs is analyzed, and a device geometry is predicted which is least sensitive to trap-assisted tunneling (TAT). The good agreement between simulated and measured transfer characteristics validates the reliability of the simulation setup. Simulations show that TAT degrades the sub-threshold swing (SS) of the t...Show More
The impact of hetero-junction and oxide-interface traps on the performance of InAs/Si tunnel FETs
2017 17th International Workshop on Junction Technology (IWJT)
Year: 2017 | Conference Paper |
Cited by: Papers (5)
The effect of traps in the hetero-junction and at the oxide interface on slope and ON-current of vertical and lateral InAs/Si Nanowire (NW) Tunnel FETs (TFETs) is demonstrated through physics-based TCAD analyses in combination with experimental findings. The high density of interface states (Dit) at the highly lattice-mismatched material interface degrades the sub-threshold swing (SS) and makes ba...Show More
How non-ideality effects deteriorate the performance of tunnel FETs
2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM)
Year: 2017 | Conference Paper |
Cited by: Papers (1)
Physics-based TCAD simulations of measured vertical and lateral InAs/Si hetero nanowire tunnel FETs are presented to demonstrate the effect of major non-idealities on slope and ON-current. The Dit limit for sub-thermal TFET operation is predicted, and it is shown that a high defect density at the InAs/Si interface can result in a slope close to 60 mV/dec due to thermionic emission in an arising MO...Show More
Modeling the Effect of Interface Roughness on the Performance of Tunnel FETs
IEEE Electron Device Letters
Cited by: Papers (5)
The sub-band formation in the triangular-like potential well in the channel of a tunnel field effect transistor (TFET) results in a delayed onset of the vertical band-to-band tunneling (BTBT) and in a reduction of the ON-current. Furthermore, the roughness of the oxide/semiconductor interface causes density-of-states (DOS) tails, i.e., a smoothing of the otherwise staircase-shaped 2D DOS in the TF...Show More
Performance predictions of single-layer In-V double-gate n- and p-type field-effect transistors
Hamilton Carrillo-Nuñez;Christian Stieger;Mathieu Luisier;Andreas Schenk
2016 IEEE International Electron Devices Meeting (IEDM)
Year: 2016 | Conference Paper |
Cited by: Papers (1)
Through ab-initio quantum transport simulations the logic performance of single-layer InAs, InN, InP, and InSb III-V compounds is analyzed in this paper for n- and p-type applications. The key findings are that (i) the low electron effective masses of all these materials lead to very similar and attractive ON-currents in n-type transistors, but cause a rapid deterioration of their sub-threshold sw...Show More
Performance projection of III-V ultra-thin-body, FinFET, and nanowire MOSFETs for two next-generation technology nodes
M. Rau;E. Caruso;D. Lizzit;P. Palestri;D. Esseni;A. Schenk;L. Selmi;M. Luisier
2016 IEEE International Electron Devices Meeting (IEDM)
Year: 2016 | Conference Paper |
Cited by: Papers (28)
Using state-of-the-art simulation tools ranging from semi-classical Monte-Carlo to full-quantum atomistic approaches, the competitiveness of III-V compounds for next-generation high-performance logic switches is confirmed. A planar double-gate ultra-thinbody (DG-UTB), a triple-gate FinFET, and a gate-allaround nanowire (NW) transistor have been designed according to the ITRS specifications for two...Show More
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