Showing 1-25 of 6,058 resultsfor "Index Terms":Hold Time
"Index Terms":Hold Time
- Sort
Get notified when new research is published matching your search criteria.
Sort By
Results
Efficient spectrum defragmentation with holding-time awareness in elastic optical networks
Elastic optical networks are prone to spectrum fragmentation, resulting in poor resource utilization and often higher blocking probability. To overcome the spectrum fragmentation, a defragmentation (DF) of the spectrum can be applied by reconfiguring some or all active connections. However, reconfiguration is generally not desirable, as it can interrupt the services of the existing connections. In...Show More
An Efficient Metal ECO Methodology for Addressing Timing Violations with 10X Turnaround Time
2022 3rd International Conference on Smart Electronics and Communication (ICOSEC)
Year: 2022 | Conference Paper |
Cited by: Papers (1)
With increased design challenges and complexity, late metal ECOs (Engineering Change Order) have become a critical and integral part of the solution cycle for tape-ins which require faster turnaround time and reduced re-spin cost. Metal ECO is a process widely adopted by major IC design houses to solve the last-minute functional and timing failures. Challenges like the limitation of pre-injected r...Show More
Timing characterization and layout of a low power differential C2MOS flip flop in 0.35μm technology
2008 2nd International Conference on Signals, Circuits and Systems
Year: 2008 | Conference Paper |
Cited by: Papers (2)
The chip developed (UltraSonic Low Voltage SAP for General Electric Medical) in co-operation of AEL (Advenced Electronic Laboratory university of Batna) and MAZ Brandenburg has been produced with 0.35 mum CMOS technology from AMS. The receiver sub-aperture processor is designed to handle the information from ultra-sonic transducer elements inside the probe handler. It performs basic analogue signa...Show More
Consequence of Various Clock Parameters on Power / Timing Analysis for VLSI Circuits
Subhadeep Nag;Suman Kalyan Porel;Dyuti Sengupta;Aniruddha Chandra;Hemanta Kumar Mondal
2024 IEEE International Symposium on Smart Electronic Systems (iSES)
Year: 2024 | Conference Paper |
Clock signals are pivotal in digital circuitry, syn-chronizing the operation of millions of transistors to achieve efficient and reliable performance. However, optimizing clock parameters is crucial for balancing power consumption and ensuring timing integrity in modern integrated circuits (ICs). This paper explores the impact of essential clock parameters such as $r$ise/fall times, setup/hold tim...Show More
Exploiting Setup–Hold-Time Interdependence in Static Timing Analysis
Emre Salman;Ali Dasdan;Feroze Taraporevala;Kayhan Kucukcakar;Eby G. Friedman
A methodology is proposed to exploit the interdependence between setup- and hold-time constraints in static timing analysis (STA). The methodology consists of two phases. The first phase includes the interdependent characterization of sequential cells, resulting in multiple constraint pairs. The second phase includes an efficient algorithm that exploits these multiple pairs in STA. The methodology...Show More
Dynamic Flip-Flop Conversion: A Time-Borrowing Method for Performance Improvement of Low-Power Digital Circuits Prone to Variations
Dynamic flip-flop (FF) conversion is a method of time borrowing (TB) for improving the performance of digital systems prone to variations. The first type of this method (Type A), which was previously presented, suffers from a large inefficient transparency window. In this brief, we present an improved structure for this method (Type B) that mitigates this problem by automatically closing the windo...Show More
Analytic study on the poles and zeros for mechanical plants
Yingying Su;Cheng Zeng;Dongshuai Kang;Xiaofeng Wang;Huabin Wang
2017 3rd IEEE International Conference on Computer and Communications (ICCC)
Year: 2017 | Conference Paper |
Cited by: Papers (1)
It is well known that controller design is often unavoidable for extreme and zero stability, and that unstable poles (zero) limit the performance of the controller. In this paper, we study the limit zeros and poles of the discrete-time model where the sampling period tends to zero in the case of zero-order hold (ZOH) or generalized sampling-data hold function (GSHF). We first introduce GSHF and gi...Show More
Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier
B. Rebaud;M. Belleville;C. Bernard;Z. Wu;M. Robert;P. Maurine;N. Azemard
2008 IEEE Computer Society Annual Symposium on VLSI
Year: 2008 | Conference Paper |
Cited by: Papers (2)
This article aims at highlighting new design issues coming from the increasing sensitivity of digital circuits towards process variability. CAD tools and current design methodologies are not anymore efficient to tackle such aspects. In particular variability is increasing the difficulty to identify setup and hold time violations. This paper is a study of failure probabilities considering device pr...Show More
Design and Analysis of a Novel Sample and Hold Architecture Based on D-Latch: Performance Evaluation and Comparative Analysis
2023 IEEE Fifth International Conference on Advances in Electronics, Computers and Communications (ICAECC)
Year: 2023 | Conference Paper |
The Sample and Hold Circuit (SHC) is a crucial component in many analog signal processing systems, responsible for capturing and maintaining the voltage level of an input signal for subsequent processing. In this paper, a novel architecture for a SHC is proposed based on a D-latch and a transmission gate, utilizing a Folded Cascode Op-Amp (FCO) as a buffer. The proposed design aims to improve perf...Show More
A comparative study of variability impact on static flip-flop timing characteristics
B. Rebaud;M. Belleville;C. Bernard;M. Robert;P. Maurine;N. Azemard
2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial
Year: 2008 | Conference Paper |
Cited by: Papers (13)
With the event of nanoscale technologies, new physical phenomena and technological limitations are increasing the process variability and its impact on circuit yield and performances. Like combinatory cells, the sequential cells also suffer of variations, impacting their timing characteristics. Regarding the timing behaviors, setup and hold time violation probabilities are increasing. This article...Show More
On the discretization of singular systems
This note proposes two new discretization methods. The proposed sampled systems are described in terms of the Markov parameters of the system and therefore the proposed methods are easily implemented. The methodology we use is a zero‐order hold discretization for the input and first‐order approximation of its derivatives.Show More
Mathematical Modeling of Arterial Blood Pressure Using Photo- Plethysmography Signal in Breath-hold Maneuver
Armin Soltan zadi;Raichel M. Alex;Rong Zhang;Donald E. Watenpaugh;Khosrow Behbehani
2018 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)
Year: 2018 | Conference Paper |
Cited by: Papers (3)
Recent research has shown that each apnea episode results in a significant rise of the beat-to-beat blood pressure followed by a drop to the pre-episode levels when patient resumes normal breathing. While the physiological implications of these repetitive and significant oscillations are still unknown, it is of interest to quantify them. Since current array of instruments deployed for polysomnogra...Show More
Haptic Rendering for Time-Variant System Based on FDTD Method Considering Realtime Discretization
IECON 2018 - 44th Annual Conference of the IEEE Industrial Electronics Society
Year: 2018 | Conference Paper |
In this paper, we present a method to rapidly discretize a continuous time-variant system in real time. Three discretization methods are compared. The proposed method does not calculate for discretization, and therefore, the calculation cost is 1/100 of that of the conventional zero-order hold model. The presented method has high stability in higher order systems and the position and size of the i...Show More
In this paper, we consider the problem of routing, modulation and spectrum assignment (RMSA) with holding time awareness in elastic optical networks. We consider a two dimensional schedule that maintains link resource usage in both spectrum and time domains, and we develop an RMSA algorithm that attempts to reduce resource fragmentation by scheduling requests in a manner that takes into account th...Show More
Comparison between first-order hold with zero-order hold in discretization of input-delay nonlinear systems
2007 International Conference on Control, Automation and Systems
Year: 2007 | Conference Paper |
Cited by: Papers (7)
In large sampling period nonlinear systems, the Taylor series method was used to improve the performance of the controller. First-order hold (FOH) and zero-order hold (ZOH) are used respectively in the discretization of input time-delay systems. The sampled-data representation of FOH and ZOH are both described. The mathematical structure of new discretization schemes are proposed and characterized...Show More
Experimental Results for Energy Harvesting by Exploiting Inherent Inadequacies of Sampling Process for IoT Applications
2020 IEEE International Conference on Communications Workshops (ICC Workshops)
Year: 2020 | Conference Paper |
Cited by: Papers (1)
Senor nodes either deployed for environment monitoring or health monitoring are battery operated, and thus energy constrained. This paper proposes a novel method for energy harvesting for the Internet of things (IoT) based applications by exploiting the inherent inadequacies of the sampling process. The sensor nodes generate a continuous-time signal corresponding to the sensed parameters, which sa...Show More
A Single Ring-Oscillator-Based Test Structure for Timing Characterization of Dynamic Circuit
Dynamic circuit is extensively used where high speed is required such as critical paths in digital and analog/mixed-signal circuits, yet it has not been successfully characterized and integrated into the digital design flows as its characterization is not straightforward due to its complex timing requirement. In this article, we first propose a step-by-step definition of dynamic circuit’s timing p...Show More
The effect of average channel holding time to estimate the QoS parameters of cellular network through guard channel scheme
Md. Asadur Rahman;Abu Shami Md. Zadid Shifat;Md. Shajedul Islam Sohag
2015 International Conference on Electrical Engineering and Information Communication Technology (ICEEICT)
Year: 2015 | Conference Paper |
Cited by: Papers (1)
Call admission control (CAC) is used to estimate the new call blocking probability and handover call dropping probability where average channel holding time is very important term to calculate these quality of service (QoS) parameters. In this research work, we have remodeled the guard channel scheme in different aspect and shown that there is some valuation faults in the conventional mathematical...Show More
Static Timing Analysis of Multibit Flipflop based LFSR
2022 6th International Conference on Computation System and Information Technology for Sustainable Solutions (CSITSS)
Year: 2022 | Conference Paper |
Cited by: Papers (3)
In the emerging VLSI technologies the industries demand for low power, area and to avoid timing violations in the digital circuits. The setup and hold timing turned out to be one of the important parameters analysed during the design of the clock routes for the digital circuits. Linear feedback shift register is a circuit used mainly in the testpattern generators. Designing a normal 8-bit LFSR wil...Show More
Static Timing Analysis of Sequential Circuit with GUI
2020 IEEE International Women in Engineering (WIE) Conference on Electrical and Computer Engineering (WIECON-ECE)
Year: 2020 | Conference Paper |
Cited by: Papers (1)
The Static time analysis (STA) used to verify the timing satisfiability of the sequential digital circuit. The occurrence of data input must synchronize with the active edge of the clock else metastable error results. A dedicated tool required to analyze the timing issue; Primetime by Synopsis. The main goal of this work is to design an STA solver with open-source technology. The methodology of co...Show More
Fixed-Time Stabilization for a Class of Time-Varying Constrained Nonholonomic Systems
Fangzheng Gao;Runjiang Yang;Jiacai Huang;Xinxin Shi;Yuqiang Wu
2020 39th Chinese Control Conference (CCC)
Year: 2020 | Conference Paper |
This paper addresses the problem of fixed-time stabilization of chained-form nonholonomic systems with time-varying state constraints. A nonlinear mapping is introduced to transform the state-constrained system into a new system without state constraints. Then, by employing switching control and backstepping techniques, a state feedback controller is successfully constructed to guarantee that the ...Show More
Feedforward Control for Track-Seeking Control in Hard Disk Drive with Sampled-Data Polynomial Based on First-Order Hold
Kazuho Igarashi;Ryo Igarashi;Takenori Atsumi;Shigeyuki Nakadai
2021 IEEE International Conference on Mechatronics (ICM)
Year: 2021 | Conference Paper |
Cited by: Papers (4)
To decrease the seek time of hard disk drives (HDDs), we proposed a feedforward control method by using a sampled-data polynomial based on a first-order hold (FOH). The proposed sampled-data polynomial satisfies the boundary conditions that include the characteristics of the FOH and compensates for the discretization error caused by the FOH without the need for complicated calculations. In this st...Show More
Designing of Control Panel for Spot Welding Machine
2018 IEEE 21st International Multi-Topic Conference (INMIC)
Year: 2018 | Conference Paper |
In this paper we focuses on designing a customized special purpose control panel that can easily control and atomize the welding process. Microcontroller based system of spot welding machine controls the operation sequence of welding starting from squeeze time through Weld, Hold and off time. Welding current along with other parameters will be the input and output will control thyristor and soleno...Show More
Channel holding time in mobile cellular networks with generalized Coxian distributed cell dwell time
Anum L. Enlil Corral-Ruiz;Felipe A. Cruz-Pérez;Genaro Hernandez-Valdez
21st Annual IEEE International Symposium on Personal, Indoor and Mobile Radio Communications
Year: 2010 | Conference Paper |
Cited by: Papers (4)
In this paper, probability distributions of new and handoff call channel holding times in mobile cellular networks are derived under the assumption that cell dwell time has generalized Coxian distribution. It is shown that when cell dwell time has a generalized Coxian distribution, the resulting residual cell dwell time has generalized Coxian distribution as well. Furthermore, both new and handoff...Show More
Analyzing BTI effects on retention registers
2012 4th Asia Symposium on Quality Electronic Design (ASQED)
Year: 2012 | Conference Paper |
IEEE Account
Purchase Details
Profile Information
Need Help?
- US & Canada: +1 800 678 4333
- Worldwide: +1 732 981 0060
- Contact & Support
- About IEEE Xplore
- Contact Us
- Help
- Accessibility
- Terms of Use
- Nondiscrimination Policy
- Sitemap
- Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest technical professional organization dedicated to advancing technology for the benefit of humanity.
© Copyright 2025 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.