GIDL Analysis of 1T1C Structure for Sub-20nm DRAM Cell

In this paper, we propose a low off-current and easily integrated MOSFET suitable for sub-20nm Dynamic Random Access Memory (DRAM). And the electrical parameters of MOS are extracted by 3D device simulation. In the same condition, the off current for the structure proposed is three orders of magnitude lower than the Partial Isolation Type Buried Channel Array Transistor(Pi-BCAT). In addition, the TCAD tool is used to construct the 3D cylinder stacked capacitor with high-k materials so that the capacitance can be more than 25fF/cell. Finally, we use the mixed mode simulation to verify the feasibility of MOSFET and the capacitor as the DRAM cell for refreshing operation.