On-Chip Power Integrity Simulation Using LSI-Core Macromodels Considering Voltage Fluctuations Caused by Inter-Function-Block Interference

When designing on-chip power distribution networks (PDNs) of a large-scale integrated circuit (LSI), power integrity (PI) must be ensured not to cause malfunctions. LSI-core macromodels are expected to be used for fast PI simulation. When building LSI-core macromodels from design information, the impedance and equivalent current sources are often extracted for each function block or smaller operating block. In the stage of modeling function blocks, the layout and operation of the surrounding function blocks are not fixed, so equivalent current sources of the macromodel of each function block are extracted under ideal power supply conditions. However, in an actual LSI, the on-chip PDNs have a certain impedance and the power supply voltage of each function block is not ideal dc voltage because of its own operation and the interference from the operation of surrounding function blocks in the same power domain. Since operating currents of transistors are affected by on-chip supply voltage fluctuations, this effect must be taken into account when simulating the PI of the entire LSI or the simulation accuracy will degrade. This article proposes a PI simulation method using LSI-core macromodels that takes into account on-chip supply voltage fluctuations due to the interference between function blocks in the same power domain. To verify the proposed method, a test chip with several function blocks was built, and it was confirmed that the proposed method can simulate PI with high accuracy.