Area and Power Efficient Design of Novel Karatsuba Double MAC (K-DMAC)

Deep learning, such as CNNs, are an essential workforce which needs increasingly high-performance hardware acceleration. Deep learning. One feature of profound workload is the intrinsic resistance to minor numerical errors and the hardware is very well suited for low accuracy. This research study suggests a new method, Karatsuba Double MAC, which aims to double the area efficiency of CNN accelerators potentially by packing two multiply and accumulate transactions (MAC) into one DSP block of FPGAs. Various technological difficulties are observed while using the CNN accelerator's mode of operation. The proposed system has been tested and analyzed by using the state-of-the-art CNN accelerator by FPGA synthesis and Verilog simulation. We notice that our Double MAC method will double the CNN layer calculation performance. The efficiency gain ranges from 14 percent to above 80 percent at network level (all convergence layers combined) depending on the CNN application and FPGA scale, over a highly optimized state-of-the-art accelerator system, without substantially decreasing its output efficiency.