Optimizing Leakage Current and Fluctuations at Ground Rail in 1-bit 8T Full Adder Circuit Using Various MTCMOS Techniques

With the technology scaling down to the nanometre regime, leakage current and resistance to noise had become important issue for the design of both combinational and sequential circuit. The efficient and widely used technique to tackle leakage current is multi-threshold CMOS (MTCMOS). However, commonly used MTCMOS technique for reducing leakage current gives rise to fluctuations at ground rail during complete reactivation from low leakage sleep to active mode transition and this fluctuation at ground rail affects the overall reliability of the circuit. Herein a low leakage eight transistor (8T) based 1-bit full adder is designed using proper sizing of different transistors. Size of transistor is calculated using optimization algorithm. Various prevalent leakage reduction techniques have been applied on optimized 8T full adder for further reduction in leakage current. Comparative analysis of leakage current as well as ground fluctuation noise is also presented by using different prevalent MTCMOS techniques. Simulation result shows that optimized 8T transistor with prevalent MTCMOS techniques achieve sub-thresholdleakage current reduction up to 62%.