Diagnosing Double Faulty Chains through Failing Bit Separation

Scan chain diagnosis plays a key role in ramping up production yield. However, this is challenged by high test compression ratios of modern designs, increasing the probability of multiple faulty chains feeding the same compressor. In our analyzed silicon data, we observe that 8.76% of scan chain failures have such two faulty chains. We propose a technique to help address this problem, separating the superposition of chain fault effects to diagnose these chips. This technique first uses jump simulation to identify and classify failures that are attributable to only one of the faulty chains. It then uses commercial tools to diagnose the classified failures of each chain individually. Experiments are conducted on both simulated and silicon test data to show the efficacy of our technique, and the proposed method showed improvements over standard diagnosis with commercial tools in resolution (2.38 candidates) and accuracy (92.0%). This method was also applied on industrial chips with potentially systematic double faulty chain failures.