RISC-V vector processor for acceleration of machine learning algorithms

In this paper we present an RTL implementation of a 32-bit parametrizable vector processor for acceleration of algorithms working in fixed-point arithmetic. The processor uses the latest RISC-V vector extension ISA specification and is deployed and tested on a Zynq Soc using Avnet Zedboard. Our microarchitecture exploits the inherent parallelism in algorithms by splitting execution across multiple vector lanes and enabling chaining of vector instructions. To provide the required number of read/write ports for instruction chaining, the vector register bank uses the double-pumping technique in combination with an XOR-based approach. First, the microarchitecture of the system is explained in detail, and the results of the implementation on the Zedboard are presented for some different processor configurations. We then compared the performance of the implemented design with some different modern processor cores.