An Algorithm for Gate Resizing to Reduce Power Dissipation in Combinational Digital Designs

Large gates are fast but dissipate more power compared to small ones. To satisfy timing constraints, large gates can be used on critical paths while small ones can be used elsewhere. In this paper, we address the problem of assigning small gates on non-critical paths under timing constraints. This problem is NP-hard. We propose a heuristic to solve it.