A Variation-Tolerant Processing-In-Memory Architecture Using Discharging Current Calibration

This paper presents a variation-tolerant ternary neural arithmetic memory (VT-TNAM) for energy-efficient processing-in-memory (PIM) accelerators. The VT-TNAM macro installs the newly proposed discharging current calibration (DCC) architecture using adjustable-current ternary bit cells (ACTBCs) to effectively mitigate local process variation. Furthermore, hierarchical MAC-operation skipping (HMS) architecture using the proposed small current detector (SCD) is also developed to compensate for energy efficiency degradation caused by MAC accuracy improvement. Successful reduction of process variation is verified using a fabricated test-element-group (TEG) in 22nm process and 20.0 – 59.2 TOPS/W is achieved by introducing the HMS architecture from analysis using the measured power of the TEG and HSPICE simulations.