A Variation-Tolerant Differential Contention-Free Pulsed Latch with Wide Voltage Scalability

As the dynamic power of electronic circuits has a quadratic dependence on the supply voltage (VDD), scaling VDD is the most effective approach to achieving low power consumption. Thus, flip-flops that can operate in a wide voltage range (from near threshold to super threshold) with minimum performance degradation are essential. However, in the near-threshold voltage (NTV) region, sequencing elements (flip-flops) suffer from unacceptably increased sensitivity to process variation, which results in significant speed degradation and functional failure. To solve the speed degradation problem, a pulsed latch can be used instead of conventional master-slave flip-flop. Thanks to its negative or near-zero setup time due to time borrowing, addition timing overhead due to setup time variation can be significantly reduced with a pulsed latch [1–2]. However, prior art pulsed latches suffer from functional failure in the NTV region because of challenging pulse-width control along with variations.