MultiCon: An Efficient Timing-based Side Channel Attack on Shared Memory Multicores

Hardware sharing in multicore processors enables massive performance improvements but brings security challenges. Adversaries exploit shared hardware for timing-based side-channel attacks and leak secret information. This paper proposes a novel multi-channel timing-based side-channel attack (called MultiCon) that exploits aggregated timing variations on shared cache, network-on-chip (NoC), and memory controller hardware in a multicore processor. Base-line cache, memory controller and NoC hardware contention attacks show sufficient timing variations, but their overall efficacy in the presence of external noise reduces significantly. De-noising schemes, such as repetition codes increase the efficacy but at the cost of slowing down the attack. MultiCon uses aggregate timing variations of multiple shared hardware resources and is less sensitive to external noise. Our evaluation on a Tile-Gx72 processor shows that MultiCon is able to achieve higher efficacy in the presence of external noise, and is >3× faster than baseline single-channel attacks.