Segmenting Age Matrices to Improve Instruction Scheduling without Increasing Delay and Area

Current superscalar processors have a special circuit called the age matrix (AM) in the issue queue (IQ), which selects the oldest ready instruction in the queue, to allow better instruction scheduling. However, the optimization level is insufficient, because the AM selects only the single oldest instruction, and the other instructions to be issued are selected randomly. In this paper, we propose a new AM organization and a scheme that uses it successfully, which we call the segmented AM (SegAM). In SegAM, the AM is physically segmented, and therefore, each AM segment is quadratically smaller than the original AM. Consequently, multiple AMs, which allow the multiple oldest instructions to be selected, can be inserted into the IQ with their total area and delay remaining unchanged or reduced from that of the single monolithic AM. To ensure that an AM segment selects the oldest ready instruction in the entire IQ, the scheme dispatches (i.e., writes) instructions to the IQ segment-by-segment, which orders the segments by age. Our evaluation results using SPEC2017 benchmark programs demonstrates that an IQ with three AMs, in which each AM is segmented into four, achieves higher performance than the conventional single monolithic AM by an average of 6.4% and 1.2% (up to 17.7% and 11.4%) for integer and floating-point programs, respectively, with reductions of 21% IQ delay, 8% IQ area, and 84% age matrix energy.